Efficient Direct Sampling and Processing Strategies
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Efficient Direct Sampling
and Processing
Strategies
Presented by
Prof Izzet Kale
Applied DSP and VLSI Research Group (ADVRG)
University of Westminster
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The Netherlands
Presentation outline
o The problem statement and motivation
o Potential advantages, challenges and
limitations
o State-of-the-art in ultra-wideband multi-giga
sample per second ADCs and DACs
o A case study of a GNSS Receiver
o How about Delta-Sigma?
o Data processor and processing strategies
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The Netherlands
The problem statement
and motivation
• The aim is to get from the high frequency real-world analog
signals 10s of GHz to the digital world in one go as quickly
and painlessly as possible.
• Once in the digital domain make use of the very many
options available to us to condition, rearrange, process and
repackage these signals for their intended destination and
use.
• The Digitally Configurable Radio (Software Defined Radio).
• Is this possible? at what price and what are the obstacles?
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The Netherlands
Potential advantages,
challenges and limitations
• Time-Interleaving can deliver very high bandwidths.
• Key aspect will be oversampled subsampled approaches
with Time-Interleaving.
• Intelligent profiling adaptively changing ADCs should be
possible with adaptively changing sampling frequency as well
as the number of interleaved paths.
• Space qualified processes and new paradigms in in-built fault
tolerant self-test self-repair structures.
• Nature of the loop filter changes the bandwidth of the
converter.
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The Netherlands
Potential advantages,
challenges and limitations
• Integrated on-chip ADC/DACs for single chip RF front-end
ADVANTAGES
• Relieves the off-chip comms and data transfer bottleneck
• Opens up possibilities to multirate and adaptive ADCs
• Enables powerful signal processing
• Matching problems and synchronisation problems are
better controlled (Adaptive DSP can come to the rescue)
CHALLENGES
• Noise, isolation, need for suitable fabrication process and
compatibility with RF and digital circuits
• Necessity for on-board high speed clock generators and
careful routing
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The Netherlands
Potential advantages,
challenges and limitations
• High speed, high resolution
ADCs are sensitive to the
quality of the clock signal.
• The SNR degrades due to
aperture jitter for a given
input frequency.
• The higher the input
frequency the higher the
sensitivity to jitter.
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The Netherlands
State-of-the-art in ultra-wideband multi-
giga sample per second ADCs and DACs
10.25 GSps 12-Bit Analog-to-Digital Converter
• Analog Device AD9213
• Two-Channel ADC (I and Q)
• Time-Interleaved Pipeline ADC
• Resolution: 12-bit
• Sampling rate: 10.25 GSps
• Power supply: 1.0V, 2.0V
• Power consumption: 5.1 W at 10GSps
12.6 GSps 16-Bit Digital-to-Analog Converter
• Analog Device AD9172
• Dual Channel
• 3 bypassable, complex data input channels per RF DAC
• Resolution: 16-bit
• DAC Sample Rate: 12.6 GSps
• Power supply: 1.0V, 1.8V
• Power consumption: 2.55 W at 12GSps
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The Netherlands
State-of-the-art in ultra-wideband multi-
giga sample per second ADCs and DACs
6 GSps 12-Bit Analog-to-Digital Converter
• Teledyne e2v EV12AQ600
• Time Interleaved selectable cores
• 12-bit resolution
• Single-channel at 6 GSps sampling speed
• Power supply: 3.3V (analog), 2.5V (I/O), 1.2V (digital),
optional 1.8V (SPI)
• Power consumption: 6.6W
7 GSps 12-Bit Digital-to-Analog Converter
• Teledyne e2v EV12DS460A
• 7GSps facilitating multi-band, direct digital synthesis12-bit
resolution
• Power supply: 3.3 V (Digital), 3.3V & 5V (Analog)
• FPGA Interface facility
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The Netherlands
State-of-the-art in ultra-wideband multi-
giga sample per second ADCs and DACs
56GSps 8-Bit Analog-to-Digital Converter
• Fujitsu 65nm CMOS technology
• Two-Channel ADC (I and Q)
• Time-Interleaved SAR ADC (256 SAR per channel)
• Resolution: 8-bit
• Two’s complement data format
• Sampling rate: 56 GSps
• Power supply: -1.2V, 1.2V, 3.3V
• Power consumption: 2W per channel (typical)
55-65 GSps 8-bit Digital-to-Analog Converter
• Fujitsu 40nm CMOS technology
• Resolution : 8-Bit
• 4 Channels (2 x IQ pairs)
• Two’s complement data format
• Sampling Rate : 55 – 65 GSps
• Power Supply : 1.8V, 0.9V, -0.9V
• Power Consumption : 0.75W/ch
• ENOB: 6.5 (-6dBFS sinewave at ~8GHz)
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The NetherlandsA case study of a GNSS Receiver
• A multi-constellation GNSS receiver should be capable of simultaneously processing multiple GNSS
signals centred at multiple frequencies.
• The University of Westminster developed a cutting-edge receiver platform, which consists of a dual-
channel RF front-end for translating the received high-frequency signals into the baseband, a DSP
for signal tracking that utilizes a FPGA, and a software suite for performing position computation by
processing the raw data from the DSP.
• The RF front-end employs sub-Nyquist sampling technique and incorporates dual-band RF filters in
order to minimize the number of RF components within the GNSS receiver. For a direct sampling
based receiver, the function of the ADC is not only restricted to the conversion of the signals from
analogue to digital domain. It is also used to intentionally alias down the RF signals to a lower IF.
ADVRG’s Dual Tracking Platform and Dual-Tracking Front-End Block Diagram
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The NetherlandsHow about Delta-Sigma?
• Delta-Sigma Modulators❖ for RF Subsampling Receivers
enable the use of 1-bit ADC.
• A Time-Interleaved Delta-Sigma Modulator in subsampled
approach can deliver very high Bandwidths.
• Reduce RF impairments in satellite radio navigation
receivers, arising from mismatches between I and Q
(phase and gain) channels applicable to low-IF or Zero-IF
(direct conversion) approaches.
• The University of Westminster receiver ❖❖ is amenable to
manufacture and attain desired yield as the function of the
entire receiver has been verified at the transistor level.
❖ A. Ucar, E.Cetin. I.Kale, “A Continuous-Time Delta-Sigma Modulator for RF Subsampling Receivers”, IEEE TCAS-II, 2012
❖ ❖ E. Cetin, I. Kale, R.C.S. Morling, A. Dempster, Satellite Radio Navigation Receiver, Patent No. US 7,839,314
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The NetherlandsHow about Delta-Sigma?
• 3rd order continuous-time Delta-Sigma Modulator
• 45nm CMOS Technology
• Sampling rate: 4GSps
• Input Signal: 2Vpp
• Input Bandwidth: 125MHz
• Resolution: 11 bits
• Dynamic range: >70dB
❖ “High Speed and Wide Bandwidth Delta-Sigma ADCs” by Muhammed Bolatkale, 2013
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The NetherlandsHow about Delta-Sigma?
• 3rd order Continuous-Time
Time-Interleaved Delta-Sigma
Modulator
• 90nm CMOS Technology
• Resolution: 13 bits
• Input Bandwidth: 20 MHz
❖ PhD Thesis In Electronic Engineering by Jafar Talebzadeh (University of Westminster)
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The NetherlandsData processor and processing
strategies
Frequency spectrum of GPS PRN 4 • Novel special non-uniform sampling,
250 120
200
100
• Suitable for CDMA systems including Galileo,
150
80
• Helps to reduce the number of samples in
the system, processing time, memory
|Y(f)|
|Y(f)|
60
100
40 requirements and power consumption,
50
20
• Uses 20 times less samples than
0
0 500 1000 1500 2000 2500 3000
Frequency (Hz)
3500 4000 4500 5000
0
0 500 1000 1500 2000 2500 3000
Frequency (Hz)
3500 4000 4500 5000
conventional approach for the same result.
FFT output with 5000 samples Novel Recovery Algorithm
output with 250 samples
Multi-element Stacking Pre-processor Scheme Digital
Beamforming Network
• A multi-element stacking scheme can be
X
used with multiple pre-processing chains
X
along with a single high bandwidth ADC which
X
is followed by a coarse channeliser to identifiy
X the stacked channels in the digital domain.
X S ADC Channeliser
X
X
X
X
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The NetherlandsData processor and processing
strategies
• Complexity reduced DSP processing for Narrowband Channelisers replacing an FIR with and
IIR based solution that has significantly lower order for a better performance.
• The Figure below shows the magnitude response of one of the 240 filters, where a 60 dB
stopband attenuation is achieved.
• This new approach does not bring in any notable contribution to the phase deviation of
individual filters and very suitable to support mobile services.
Magnitude Spectrum and Phase Spectrums of a Single Channel
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The NetherlandsData processor and processing
strategies
• The same can be accomplished for a broadband channeliser. For maximal flexibility one must
be able to select any combination of 240 channels and glue them together.
• The deviation throughout the magnitude spectrum is no larger than 0.3 dB.
• On the other hand, the phase distortion is present only at the transition between adjacent
channels
Magnitude Spectrum and Phase Spectrums of a the combined spectrum
Workshop on High End Digital Processing Technologies and EEE Components for Future Space Missions (HEDPT)
Monday 1st October 2018 at ESA-ESTEC in Noordwijk, The NetherlandsTHANK YOU FOR LISTENING
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