(My) highlights of ATLAS Phase II strips tracker meeting at Valencia - Sergio Díez Cornell 18 Feb 2014

(My) highlights of ATLAS Phase II strips
      tracker meeting at Valencia
             Sergio Díez Cornell
                18 Feb 2014

Meeting timetable

 Half a day of 250 nm prototype activities

 A full day of 130 nm ASICs and modules electrical

 Half a day of stave/petal local support

 A full day of organization structure

 Half a day of simulation and layout

 Half a day of integration (global support, installation)

  18 Feb 2014                  S. Díez, Highlights of Valencia strips meeting   2

Meeting timetable

 Half a day of 250 nm prototype activities

 A full day of 130 nm ASICs and modules electrical

 Half a day of stave/petal local support

 A full day of organization structure

 Half a day of simulation and layout

 Half a day of integration (global support, installation)

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Phase II strips tracker organizational chart

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ITk roadmap

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250 nm program: full length DC-DC stave
 Single-sided DC-DC stave completed at RAL

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250 nm program: full length SP stave
 SP stave core:
     Tape manufactured at Altaflex Inc. and
      surveyed at LBL (Carl, Brian)
     Core manufactured at Yale, BNL and
      surveyed at LBL (Carl, Haichen)
     Shipment to RAL for module assembly with
      no damage
 4 modules already placed at RAL
     SP provided by (new) SP protection boards
      (SPP)
     Hookup mistake on SPP board
            • Several modifications needed (ongoing)

                                 2V5               0V

        SPout                                                                               SPin

                                 SPout     SPin
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250 nm program: endcap petalets (I)
 Petalets: shortened versions of endcap petals, double-sided, mimic sensor splitting on
  central area of petal
      Two versions of petalets, depending on power/data routing and size of hybrids

   Modules OK, first petalet just assembled                                      Hybrids OK, tapes and modules soon

         Only DC-DC power so far
         Sensors produced at CNM Barcelona with standard and embedded (double metal) bonding pads
         Custom End of Petal (EoP) boards
         Cores and mounting tools ready
    18 Feb 2014                               S. Díez, Highlights of Valencia strips meeting                          8

250 nm program: endcap petalets (II)

 First petalet just assembled
      Single top hybrid, standard pads
      Noise and readout issues, ongoing work

                                                          Second petalet: lower module assembled
                                                                   Single top hybrid, embedded pads
                                                                   Same noise issues, ongoing work

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Plans for 250 nm completion
 Finish full length SP stave

 Populate second side of full length staves

 Finish 10 petalets (singe hybrid, double hybrid, standard pads, embedded pads)
      Come out with a single layout (single or double hybrid) and move on to 130 nm

 Irradiations and comparison of standard and embedded pad sensors for petalets

 Test beam studies on double sided petalet

 CO2 cooling tests on full length staves

 SP studies for petals on a bigger prototype (full length petal, 130 nm)

 Noise injection tests on power lines and cooling pipes

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What’s wrong with the new ABCN 130 ASIC?
 XOFF and DATA are bidirectional lines
      Control data flow on the serial chain between chips and the HCC (outside world)
             • XOFF determines if the chip is ready to receive (or send) data from (to) the adjacent chip
             • DATA is the line to which the data is sent (or received) if the corresponding XOFF gives the OK
      There are left and right lines, which can be set to be Drivers (D) or receivers (R)
             • i.e., If XoffR is a D  then DataR is a R, XoffL is a R and DataL a D
                    One single bit controls the driver or receiver state of these lines on a chip, “dir”
                    This same bit controls the associated function for XOFF and DATA on the core logic

                           L                   R

   18 Feb 2014                               S. Díez, Highlights of Valencia strips meeting                      11

What’s wrong with the new ABCN 130 ASIC?
 This same bit controls the associated function for XOFF and DATA on the core logic
      It makes sense, but…
      The bit is always flipped, no matter which state you choose
             • If XOFF is a driver, it is set as “sending 0”, if it is a receiver, it is set as “Not listening”
             • Same thing for DATA

                 What it should be                                                                What it is

                                                      dir                                                         dir

                         dir                          dir                                          dir            dir

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ABCN 130 fix
 Focused Ion Beam (FIB) to correct polarity
  of driver/receiver state of XOFF and DATA
      Open passivation layers
      Cut each line
      “Draw” metal contact
 One day per chip, ~ 2000 $ /ASIC for
  just one side of the chip

   18 Feb 2014                   S. Díez, Highlights of Valencia strips meeting   13

ABCN 130 test results
 Single chip test boards and software developed
 4 chips FIBed and re-tested at UK
      3 of them worked after repair
      Lower power than expected (~ 9% lower), to be
       confirmed at higher clock rates (160, 320 MHz)
      Slightly lower gain than expected
              • 70 mV/ fC observed, 90 mV/fC expected
      Trimming possible
      Decent noise performance up to 7 fC
                                                                                            Response curve up to 7 fC

 I analogue          54 mA

  I digital          33 mA

   Total I           87 mA

  I/channel         0.34 mA

  P/channel         0.51 mW

   18 Feb 2014                             S. Díez, Highlights of Valencia strips meeting                           14

Future ABCN 130 ASIC
 Learn as much as possible from current chips
     FIB 5 ASICs, make a shortened hybrid version
     External calibration charge measurements to understand low gain
 Redesign, correct, recheck, resubmit
     5-7 weeks from now

   18 Feb 2014                       S. Díez, Highlights of Valencia strips meeting   15

ABCN 130 module components and assembly
 Lots of progress with thermo mechanicals and dummies (bonding, gluing, mounting
  jigs, testing jigs,…)

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LV powering: New DC-DC converters

                     New module topology requires new
                      converters geometry                             8 mm
                              Identical functionality as current
                               converters, plus sensor HV filtering

                                                                              43.75 mm
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DC-DC converter with planar coil
 Developed by Yale using mostly commercial
  components
     Significant reduction in height
           • Easier integration and cooling
     Similar or superior noise performances on
      ABCN25 modules compared to current
      converters
     Also requires shielding
     Lower efficiency due to proximity of shielding
      to coil (inductance decreases)
     Ideally would like to maintain efficiency of
      current converters with planar coils
           • Some ideas already being sketched
     Ideally, one would use a planar coil with custom
      ASIC present in current converters

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LV powering decision
 Route to a powering decision
     Look for significant differences in “standard” test results
            • ENC, NO, DTN
     Look for susceptibility to external noise signals
            • On LV inputs, pipes, etc
     Which powering option is better for our material budget?

     Test staves with ABC-130 with serial power and DC-DC
            • Fully loaded on one side and partially loaded on the other side
     One solution for the barrel and EC unless there were extremely compelling reasons
     A serial powering design should be evaluated for the EC petals

 Timeline: ~ Q2 2015

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Test of Fast Cluster Finder features

 DAQ hardware and test setup developed at LBL
  (Eric, Silvain)
 FCF correlator logic and test interface ready
  (Lorenzo)
 Could also be a good alternative to test ASICs
  using FCF lines
 Still struggling to get the chips to respond

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Moving towards bigger objects
 Stave 130 geometry well established
 Petal geometry still has many unknowns
      11 different modules on a petal!
      Many options, none of them very nice: straight or curved
       hybrids, straight sensor pads, curved strips, strips with
       different lengths within each sensor,…
      Design and manufacture all different ABCN130 hybrid
       flavors during the next year

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Tons of other topics…
     HV powering: irradiation campaign and selection of technology
     130 nm bus tapes: one single flavor for both power distributions, both axial and stereo
     Layout for pure electrical EoS well advanced
     Investigation of orbital welding and electrical break on cooling pipes
     Honeycomb gluing and defect modeling for honeycomb-fiber delamination
     Stave core QA studies
     New measuring techniques for defects on staves and petals (Carl’s LDRD)
     New stave core assembly jig
     New optical package for opto links (“lightpeak”) in development
     Mechanical tests on petal prototypes
     Future FEA studies on staves and petals
     Barrel and endcaps global structures and assembly
     Type-I services for barrel and endcaps

    18 Feb 2014                      S. Díez, Highlights of Valencia strips meeting        22

Simulation session
 A morning session of simulation studies (not summarized in this talk)
         Hit requirements (number of layers)
         Occupancy
         Influence of material
         Alignment
         Current status of simulations
 Asked for needs from the upgrade strip community
      High priority simulation studies
             • Endcap strip simulation (this is a bottleneck on simulations)
             • Study dropping stub
      Medium priority simulation studies
             • Study dropping end cap disk
             • Drop stereo layer study needs tracking experts
      Strip community to provide list of failure modes, ITK-SIM to study effect
      Efficiency/ fake rate as a function of Nhits/ExpectedHits
      Use extra material samples to study occupancy near jets
 Improve interaction with trigger group
 Need to be careful planar sensor priorities aren’t dropped for CMOS

   18 Feb 2014                                S. Díez, Highlights of Valencia strips meeting   23