CLOSED LOOP SPEED CONTROL OF INDUCTION MOTOR USING - Journal of ...

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Vol 12, Issue 06, JUNE / 2021
                                                                         ISSN NO: 0377-9254
       CLOSED LOOP SPEED CONTROL OF INDUCTION MOTOR USING
                      MULTILEVEL INVERTER
                    Vadthiya Keerthi                             Dr.G.Annapurna ,Assoc.Professor
 Department of Electrical and Electronics Engineering   Department of Electrical and Electronics Engineering

 G. Narayanamma Institute of Technology and Science, G. Narayanamma Institute of Technology and Science,
              Hyderabad, Telangana, India                           Hyderabad, Telangana, India
              Keerthivadthya@gmail.com                                 gootyanu@gmail.com

ABSTRACT - Induction motors have recently                bridge and Diode clamped inverters Using
gained a major foothold in automotive drive              MATLAB/SIMULINK tools.
systems, displacing the DC motors that were
                                                         Keywords- Multilevel, harmonic, cascade H-bridge,
formerly used. There are many methods for
                                                         diode clamped, carrier based pulse with modulation
controlling the speed of an induction motor, the
most common of which is the V/F method, which is         I INTRODUCTION
widely used in industrial and domestic applications
due to its simplicity. This paper absorbed on               These are commonly used in industry to monitor
implementing the closed loop speed control of an         conveyor system speeds, blower speeds, machine
induction motor using V/f method. The control is         tool speeds, and other applications that include
obtained by keeping the ratio V/F constant.              variable speeds. AC motors, especially Induction
                                                         motors, are favoured over DC motors in most cases
    Harmonics were to blame for the low output of        due to their low cost, low maintenance, lower
voltages and currents in a traditional inverter fed      weight, higher performance, better ruggedness and
induction system. If the level of the multilevel         reliability. All of these characteristics allow
inverter rises, the stepped waveforms get closer to      induction motors to be used in a wide range of
the sinusoidal of lower harmonics. The most              industrial applications. The quality of the output
practical topologies of multilevel inverter to use as    voltage determines the performance characteristics
a power converter for medium and high power              of induction motors; he quality of the output line
applications are cascaded H-bridge and diode             voltage varies depending on the kind of inverter. In
clamped multilevel inverter. Multilevel perspective      order to achieve a steady, constant and step less
give case of control, high voltage capability, good      variance in motor speed, advancements in Power
power quality, low switching loss. The speed of the      Electronics and semiconductor technology have
induction motor can be adjusted by properly              prompted the invention of high power and high
regulating the duty cycle of PWM pulses and using        speed semiconductor devices. The presence of
a V/F control system. The most common carrier-           harmonics causes the output current and voltage of
based PWM strategies are introduced, including           an induction motor fed by a traditional two-level
sinusoidal PWM, third harmonic injection PWM             inverter to be of low quality. The existence of a large
and space vector PWM. Sine pulse width                   number of harmonics causes extreme torque
modulation is a commonly used technique for              pulsations in the motor, particularly at low speeds,
various inverter topologies and the same is              which manifest themselves as shaft cogging. It can
employed in this project.                                also result in unwanted motor heating as well as
   It is proposed to achieve speed control of            electromagnetic disturbances. The reduction of
induction motor using closed loop V/F control.           harmonics necessitates the use of massive filters,
Which employs three and five level cascaded H-           which increases the system's size and expense.
                                                         Multilevel inverters are now a viable and cost-

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                                                                          ISSN NO: 0377-9254
effective option for medium-voltage and high-
power applications. With advances in power
electronics and microelectronics, multilevel
inverters, which increase the number of levels of the
inverters rather than the size of the filters, it is now
possible to reduce the magnitude of harmonics. If
the number of levels in a multilevel inverter grows,
the inverter's output improves.
P, PL PID controllers are a common traditional
controller. The PI controller is one of them, and it is
frequently utilised by researchers as the best
controller for their applications. This approach is        .
utilised in this study for closed loop speed control.
The PI controller is utilised to transform the error       Fig. 2.1 five Level Flying Capacitors Multilevel
signal to the actual signal in this feedback loop.         Inverter
A multilevel inverter fed three-phase induction
motor drive is presented in this paper. To investigate     DIODECLAMPED MULTILEVEL INVERETER
the reduction of harmonics, the FFT spectrums for              The first practical multilevel topology was the
the outputs are examined. MATLAB/Simulink is               neutral-point-clamped (NPC) PWM topology.
used to simulate induction motor speed modulation          Clamping diodes are used in diode clamped
for three-phase three and five stage diode clamped         multilevel inverters. It aids in the reduction of
and cascaded H-bridge multilevel inverters.                voltage tension in control electronic devices. It's
II MULTI LEVEL INVERTER TOPOLOGIES                         often referred to as a "neutral point adapter." A
                                                           diode clamped inverter with ‘m’ levels requires (m-
    The Multilevel inverter is used in commercial          1) switch pairs.
applications as a high-power, medium-voltage
solution. Multilevel converters are classified as
cascaded H-bridge Inverters, diode clamped
inverters and flying capacitor Multilevel inverters.
FLYING CAPACITORS MULTILEVEL
INVERTER
    The use of capacitors is the core idea behind this
inverter. It consists of a series of capacitor clamped
switching cells connected in series. Electrical
instruments receive a small amount of voltage from
the capacitors. The switching states of this inverter
are similar to those of a diode clamped inverter. This
kind of multilevel inverter does not require
clamping diodes. The output voltage is half of the
DC voltage supply. It's the drawback in the
multilevel inverter with flying capacitors. In order
to stabilise the flying capacitors, it also has            Fig. 2.2 Single Phase Five Level Structure of a
switching redundancy within the process. It has the        Diode Clamped Inverter
ability to monitor both active and reactive power
                                                           Table I. Switching States of Diode Clamped
transfer. However, switching losses will occur due
                                                           Inverter
to the high-frequency switching.
                                                               Output    S1 S2 S3 S4 S5 S6 S7 S8
                                                               voltage

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 Vdc           1       1       1        1       0    0    0   0   voltage clamping diodes or voltage balancing
 3Vdc/4        0       1       1        1       1    0    0   0   capacitors. This setup is ideal for constant frequency
 Vdc/2         0       0       1        1       1    1    0   0   applications including active front-end rectifiers,
 Vdc/4         0       0       0        1       1    1    1   0   active power filters, and reactive power
 0             0       0       0        0       1    1    1   1
                                                                  compensation. A specific harmonic in the output
                                                                  waveform can be eliminated by selecting suitable
CASCADED               H-BRIDGE                     MULTILEVEL    conducting angles for the H bridges.
INVERTER                                                              The diode clamped and cascaded H-bridge
    Separate DC sources or capacitors are used in                 outperformed the flying capacitor among three
the cascaded H-bridge inverter. It just necessitates a            multilevel inverters. The voltage regulation of the
smaller number of components in each level. The                   flying capacitor is difficult due to the large number
power conversion cells are connected in sequence.                 of capacitors and low switching power. The diode
The H-bridge is made up of a pair of capacitors and               clamped and cascaded H-bridge multilevel inverters
switches. A different input DC voltage is obtained                are employed in this work.
for each H Bridge. It produces a sinusoidal voltage
as an output. The Inverter is made up of three H-
bridge cells that are paired in series and have three             III SINUSOIDAL    PULSE                     WIDTH
distinct levels of DC voltage (zero, positive DC and              MODULATION TECHNIQUE
negative DC voltages). The output voltage is equal                    The duty cycle of switches can be cleared using
to the sum of the voltages provided by each H                     special PWM techniques to generate output voltage
Bridge cell. The number of output voltage levels                  in multilevel inverters. As a result, a proper
depicts a single step cascaded H Bridge Inverter.                 switching transformation is selected with the aid of
                                                                  a controller in order to create the desired output
                                                                  voltage. SPWM, a recently adopted technique, is
                                                                  used to supply gate signals to these control switches
                                                                  in this work.
                                                                      The phase-shifting technique is used to minimise
                                                                  harmonics in the load voltage in carrier-based
                                                                  sinusoidal PWM (SPWM). For M level output, (M-
                                                                  1) carrier waves are used in carrier-based PWM
                                                                  schemes. There are two types of carrier-based PWM
                                                                  schemes: (I) phase-shifted multi carrier modulation
Fig. 2.3 Single Phase Cascaded H-Bridge                           and (ii) level-shifted multi carrier modulation. There
Multilevel Inverter                                               are three types of level shifted multi carrier
Table II. Switching States of Cascaded H-Bridge                   modulation schemes: (I) in phase disposition, (ii)
Inverter                                                          alternative phase opposite disposition, and (iii)
                                                                  phase opposition disposition. In this work, in phase
 Output    S1 S2 S3                S4       S5       S6   S7 S8   disposition is employed.
 voltage
 0         0       0       0       0        0        0    0   0   A. SPWM for phase disposition (PD SPWM)
 Vdc/2     1       0       0       1        0        0    0   0       Many of the carrier signals are in phase and level
 Vdc       1       0       0       1        1        0    0   1   transferred in this SPWM technique. The pulse
 -Vdc/2    0       1       1       0        0        0    0   0   generation theorem for five-level PD SPWM is seen
 -Vdc      0       1       1       0        0        1    1   0
                                                                  in Figure 3.1 C1, C2, C3, and C4 are the carrier
                                                                  signals, while Vr, Vy, and Vb are the three-phase
   Each bridge's AC terminal voltages are linked in               reference or modulating signals. The control signal
sequence. The cascaded inverter, unlike the diode                 is produced by comparing these four carrier signals
clamp or flying capacitors inverters, does not need               with the corresponding modulating signal, and it

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                                                                                        ISSN NO: 0377-9254
must be provided to the phase-leg devices
corresponding switches

                                                        Fig.3.3 Phase   opposition                                                disposition
                                                        SPWM (POD SPWM)
                                                        IV.SPEED CONTROL OF INDUCTION
                                                        MOTOR

   Fig. 3.1 Phase Disposition SPWM (PD SPWM)                The Induction motor can be simulated using
                                                        open loop control and closed loop control method.
B. Alternate phase opposition disposition               Desired speed range can be achieved by processing
SPWM (APOD SPWM)                                        the error between the actual speed and set speed
     It's similar to the PD SPWM strategy, but the      using PI controller for the closed loop. Whereas in
carriers are phase shifted 180 degrees in opposite      open loop control, based on the load on the motor,
directions, as seen in Fig 3.2                          the speed of the motor will vary. In this project,
                                                        closed loop speed control of induction motor is
                                                        studies by variable speed is applied in closed loop
                                                        system while the load can be constant or variable.
                                                        V. SIMULATION RESULTS

                                                        Table. III Total Harmonic Distortion(THD)
                                                        of Multilevel Inverter
                                                         NAME OF THE MULTILEVEL           THREE LEVEL         FIVE LEVEL          SEVEN LEVEL
                                                         INVERTER

                                                                                           Phase    Line      Phase     Line      Phase     Line
Fig:3.2 Alternate Phase Opposition Disposition                                            voltage   voltage   voltage   voltage   voltage   voltage

SPWM (APOD       SPWM)
                                                         Diode Clamped Multilevel         82.77%    42.48%    29.78%    18.35%    18.18%    10.77%
C. Phase opposition disposition SPWM (POD                 Inverter THD Analysis
SPWM)                                                    Cascaded H-bridge Multilevel     55.56%    36.34%    27.13%    17.7%     18.15%    6.31%
     The carrier signals above the reference/zero        Inverter THD Analysis

line are in phase with each other, as are the carrier
signals below the zero line, but the carriers below
and above the zero line are 180 degrees out of          Closed Loop Speed Control of Induction Motor
phase, as seen in Fig 3.3                               Simulation Diagrams Fed from 3 level and 5
                                                        Level Inverter of Both Topologies I.e. Diode
                                                        Clamped and Cascaded Are Presented Below

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                                                              ISSN NO: 0377-9254

                                               5.4 closed Loop Speed Control of IM Fed Form
                                               Three Level Cascaded H-Bridge Inverter
5.1 closed Loop Speed Control of IM Fed Form
Three Level Diode Clamped Inverter

5.2 Speed Curve of IM Fed Form 3 Level Diode   5.5 Speed Curve of IM Fed Form 3 Level
Clamped Inverter                               Cascaded H-Bridge Inverter

                                               5.6 Speed Curve of IM Fed Form 5 Level
5.3 Speed Curve of IM Fed Form 5 Level Diode   Cascaded H-Bridge Inverter
Clamped Inverter
                                               VI. CONCLUSION
                                                   The Total Harmonic Distortions of output
                                               voltages from three level, five level and seven level

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                                                                        ISSN NO: 0377-9254
diode clamped and cascaded inverters were                 7. T. Adam. "Different PWM modulation
compared using FFT analysis. As compared to a             techniques indexes performance evaluation" , ISIE
diode clamped inverter, the harmonics of a cascaded       93 - Budapest IEEE International Symposium on
inverter output voltage are the least. Simulation         Industrial Electronics Conference Proceedings,
results reveals that with the open loop voltage           1993
control, the output voltage is not regulated and it
varies with the fluctuations in the input voltage. This
can be overcome using closed loop voltage control,
when the output voltage is regulated irrespective of
the fluctuations in the input voltage. In order to meet
the constant voltage requirement, the closed loop
control is proposed. The performance characteristic
of diode clamped and cascaded H-bridge Inverter
fed three phase induction motor is evaluated and it
is found that, it gives better response and
considerably less THD.
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