SOI pixel detector Toru Tsuboyama (KEK IPNS, Sokendai) For the SOI pixel tracker group 17 Mar. 2021 WG-2 AFAD2021 meeting on-line - Indico
←
→
Page content transcription
If your browser does not render page correctly, please read the page content below
Novosibirsk Mammoth Museum
SOI pixel detector
Toru Tsuboyama (KEK IPNS, Sokendai)
For the SOI pixel tracker group
17 Mar. 2021
WG-2 AFAD2021 meeting on-line
The work is supported by the Kakenhi grand-in-aid fund, JSPS, Japan
Outline
• The Belle-II vertex detector
• SOI pixel sensor technology
• Improvement of the SOI technology
• DuTiP: The pixel sensor for the Belle II
The DuTiP development team
upgrade
T.TsuboyamaA, J.Haba AB, Y.Arai A,
• Summary M. Ishikawa A, I. Kurachi A, T. Takayanagi A, T.
Miyoshi A, Taohan Li B, M. Yamada C,
Baudot Jérome D, Kachel Maciej D,
and SOI collaboration.
KEK A, Tohoku B, TMICT C, IPHC Strasbourg D
AFAD2021 17 March 2021 T.Tsuboyama 2
SuperKEKB project
• KEKB is a 7 GeV + 4 GeV e+e-
asymmetric energy collider.
• Study mainly B meson decays such
as " #
! ! → Υ 4' → (( → Hadrons
to study details of the CP violation
in the B meson decay.
• Deviation from the standard model
indicates the effects from the new
physics such as Super Symmetric
Model.
• Design luminosity: 6x1035/cm2/s
• Operation started in 2019 AFAD2021 17 March 2021 T.Tsuboyama 3
Belle II detector 8m
• To identify B mesons, the particles in the
final state should be all detected and
identified the particle species.
8m
! " # $% $& $ ± ( ) *
• The vertices of two B mesons should be
identified and measured. à a good vertex
detector is necessary.
• High Physics Event rate 3 kHz @ design
luminosity Contributions from Russia
• Run schedule has not been affected by the Physics analysis
Corona virus pandemic, thanks to CsI calorimeter
tremendous efforts by collaborators. KLM KL muon system
AFAD2021 17 March 2021 T.Tsuboyama Visiting Scientists staying in Japan
4
Belle-II vertex detector
Main purpose: Identify and measure the two B vertices
Successful in KEKB (1999-2010)
For Belle II, the R&D started around 2008
Production 2012-2018
Installation to Belle2 2018 November
L6 DSSD Japan/Korea
L5 DSSD Austria
L3 DSSD Aust L4 DSSD
ralia India
L1/2 Pixe
l Germany ⌀ 30 cm
Support structure KEK 70 cm
Electronics Austria (HEPHY)
Power supply INFN (Italy)
AFAD2021 17 March 2021 T.Tsuboyama 5
SuperKEKB Upgrading activity
• The SuperKEKB is improving the
luminosity.
• To achieve the goal, modification of the
accelerator is planned in 2026-2027.
• The Belle II upgrade discussion has started
aiming the installation in the same period.
• The current pixel vertex detect is made
with DEPFET pixel sensor, whose
integration time is 20 µs and will be
difficult to keep the physics performance
in the high background condition.
• The upgrade of the pixel detector is one of Further luminosity upgrade is discussed assuming
6x1035/cm/s is achieved.
the key issues.
6
SOI/ Silicon on insulator
• Originally, a CMOS device technology.
• MOS transistors are isolated and thin: Low Capacitance.
• Easily controlled with low power consumption.
• A monolithic pixel detector can be made if the signal induced in the wafer is
processed by the CMOS circuit.
• The standard CMOS design cad tools can be used for the circuit and sensor
design. PMOS NMOS
Buried Oxide (BOX)
Charge collection Fast because the sensor is depleted with bias Buried P Well (BPW)
voltage.
Ch
Monolithic The signal in the wafer is directly connected to holes
arg
depletion
e
the MOSFET
dp
region
art
Radiation hard Discuss later
icle
n- substrate
s
CMOS circuit Complex circuit can be implemented by using
standard ASIC tools. AFAD2021 17 March 2021 T.Tsuboyama 7
AFAD2021 17 March 2021 T.Tsuboyama 8
The structure of an SOI sensor
Metal 5
Circuit Metal 4
Metal 3
Metal 2
Gate
Metal 1
BOX (buried Oxide 200nm thick)
Contact to the wafer (sensor)
Sensor
SOI Silicon for the MOSFET 40nm thick
The gate oxide (4 nm17thick)
AFAD2021 is too
March 2021 thin to be identified
T.Tsuboyama 9
In fact, this is a DSOI photo
3D integration technology (1999)
• In order to increase the pixel functions 3D integration of LSI
to the pixel detector is tried.
• The first result was made just after the AFAD 2019 meeting.
• Micro bumps were made on two chips and assembled to
one sensor.
• 30,000 connections were made in a chip.
• > 99.9% connection yield was confirmed.
• The Performance is confirmed by a beam test
Si
AFAD2021 17 March 2021 T.Tsuboyama
Sensor silicon Sensor 10Requirements to the pixel detector
• For the physics performance, spatial resolution of 10 µm and the sensor
thickness < 75 µm (minimize the multiple scattering and charge sharing) is
required.
• To cope with the high luminosity and beam backgrounds in Belle2
environment, high timing resolution is quite important.
Luminosity 4 1036/cm2/s
Expected background hit rate 113 MHz/cm2
Level 1 trigger rate (peak) 150 kHz
Trigger decision (latency) > 5 µs
Pixel Occupancy < 0.1%
Pixel size (*) < 45 µm × 45 µm
Sensor thickness (*) < 100 µm
Low power consumption For easier cooling 11Reduction of background hits (i) Small pixel size
• Our goal is to keep the hit occupancy < 0.1 %.
• Hit occupancy: The rate of background hits entering a pixel per event.
• To reduce the hit occupancy, there are two keys
1. Small pixel size
2. High timing resolution and coincidence
• The pixel size is a trade off with the pixel function and spatial
resolution.
• We chose 45 µm x 45 µm pixel which can achieve a spatial resolution of
about 10 µm.
• (113 MHz / cm2) x (45µm x 45 µm) = 2.3 kHz
• We still need a function to select hits from the beam background.
AFAD2021 17 March 2021 T.Tsuboyama 12Reduction of background hits (ii) Coincidence
• In order to select the real hits from backgrounds, coincidence with the
trigger signal is very powerful.
Signal_in_pixel
Trigger
Output
• We need
• A good time resolution
• Delay for the trigger decision
AFAD2021 17 March 2021 T.Tsuboyama 13Reduction of occupancy
Trigger latency
• DuTiP utilizes 16 MHz clock for coincidence
and two clocks for the coincidence window.
• Trigger Latency: The Belle arrives to the pixel
sensor 5-10 µs after the event happens.
• A delay timer is necessary in each pixel to keep
hit information for the latency. Global
Trigger
Delay
ALPIDE Coincidence Hit 0
circuit
1
4DuTiP: Dual Timer Pixel
• The second hit arriving to the pixel within the
trigger latency will be ignored if there is only one
timer. Trigger latency
• Probability is (Latency)/(Average hit interval) ~ 2%.
• The 2nd hit is handled with the 2nd Delay logic.
2nd hit
• The hit pixels are read out by the scanning logic.
• HIt information is transferred to the readout FIFO Hit 0
and sent to the data acquisition system
Hit 1
2nd coincidence
Scanning
Global Trigger
logic
Delay
Coincidence Hit 0
circuit 0
Diode ALPIDE
Delay
Coincidence Hit 1
circuit 1
Readout
FIFO 15DuTiP1 chip Pixel Layout
• The DuTiP scheme do not assume the production 45 µm
technology, although, full CMOS circuit will be used.
7-bit Timer 0
• DuTiP1 chip
• Lapis 0.2 µm SOIPIX technology with PDD structure
• Pixel size 45 µm x 45 µm 7-bit Timer 1
• The first prototype was submitted in Nov. 2020.
• Delivery: Spring 2021. → Evaluation in FY2021.
• Sensor size: 6 mm x 6 mm.
ALPIDE
Readout /
sequencer
• Delay is made with a 7-bit Counter with 16 MHz
clock.
• Max Delay (trigger latency) = 8 µs,
• Coincidence window = 60 ns + 60 ns (for trigger timing
jitter). Designed by T. Takayanagi
DuTiP1
16Summary
• Under difficult condition Belle II is running efficiently
• In order to cope with high background at the design luminosity detector
upgrade is planned.
• The SOI technology provides a high performance pixel sensors for
scientific researches.
• After 2019
• For the pixel detector, we propose a SOI based pixel sensor: DuTiP
• The standard CMOS design tools are used to design the sensors.
• I will be happy I can report the result in AFAD again.
AFAD2021 17 March 2021 T.Tsuboyama 17If you are interested in the SOI
• Please visit
• http://soipix.jp or http://rd.kek.jp
• And send us mail
• toru.tsuboyama@kek.jp or yasuo.aria@kek.jp
AFAD2021 17 March 2021 T.Tsuboyama 18Back up
AFAD2021 17 March 2021 T.Tsuboyama 19ALPIDE type analog input circuit
• The amplifier designed for ALPIDE pixel sensor for ALICE experiment is
adopted.
• Signal charge from the sensor (Q) is converted to voltage (Vin) with the
detector capacitance (Cdet): Vin=Q/Cdet.
• Small Cdet is realized with monolithic sensors.
• The circuit contains a voltage amplifier and a discriminator.
• Low power consumption: We designed each channel consumes: 360 nW/pixel
or 0.02 W/cm2.
Q
Cdet 20Historical Pixel detectors
CCD φ1 φ2 φ3 φ1 φ2 φ3
readout CMOS/MAPS
Charged particles
n+ PMOS PMOS
e e e e e
n+ n+ n+ n+
N-well
3-10 μm P-well
Ch
electrons
ns
arg
p- epi
ctro
3-10 μm
ed
par
p- epi
ele
ticl
p substrate p- substrate
es
Hybrids
Charge collection complex circuit
Readout chip
CCD Diffusion NO
CMOS Diffusion NO
Bumps
DEPFET Drift NO
Sensor
HV CMOS Drfit YES
electrons
Depleted
Hybrid Drift YES
SOI Drfit YES
In general, sensors with diffusion read out is weak to the radiation effect compared
with sensors with the depletion layer.
AFAD2021 17 March 2021 T.Tsuboyama 21Pixel sensor for the Super KEK B factory
• The current pixel detector for the Belle2 is made with DEPFET sensors.
• 2018 run data showed that
• An impact resolution of 12 µm (expectation 10µm) is achieved.
• Pesimistic extrapolation of the hit occupancy to the luminosity goal would exceed 3%.
• The performance of the sensor will be spoiled by the background hits.
• Usually, occupancy should be suppressed 0.1% level.
• Discussion of detector upgrade started in February.
pT > 1 GeV
# CDC hits > 20
# SVD hits ≥ 6
AFAD2021 17 March 2021 T.Tsuboyama 22PIXOR for the Super KEK B factory
• To cope with the high hit rate, SOI pixel is an
attractive candidate.
• Pros.
• Fast charge collection
• Fast shaping time
• Data suppression on chip
• Reduction occupancy and bandwidth of the data acquisition
system
• Cons:
• Power dissipation.
• Increase of material for the cooling.
AFAD2021 17 March 2021 T.Tsuboyama 23PIXOR concept
• If the pixel is hit, the comparator initiate the down counter.
• At the timing of trigger latency, the hit coincidence is taken and
hit output is raised.
• Analog data is not read out for the power saving.
• The pixel size is reduced to maintain the spatial resolution.
• In order to reduce occupancy from 3% (DEPFET) to 0.1% or less,
the shaping time T should be 0.5 µs or less.
• T=0.1 µs is preferred for the safety margin.
Analog part Digital part
9-bit
Preamplifier Shaper Sequencer down Trigger
counter
Discriminator compare
idle
CLK
count
== 0
count
Out
Sensor
node load
Threshold 4-bit Trigger
Vdet voltage Trim Trigger
AFAD2021 17 MarchDAC
2021 T.Tsuboyama
latency 2 sets 24You can also read
