Design-Aware Parasitic-Aware Simulation Based Automation and Optimization of Highly Linear RF CMOS Power Amplifiers
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electronics
Article
Design-Aware Parasitic-Aware Simulation Based Automation
and Optimization of Highly Linear RF CMOS Power Amplifiers
Rana Aly Onsy *, Mohamed El-Nozahi and Hani Ragai
Electronics and Communications Department, Faculty of Engineering, Ain Shams University, Cairo 11566, Egypt
* Correspondence: ranaaly83@gmail.com
Abstract: In this paper, a parasitic-design-aware simulation-based design tool is proposed for highly
linear RF power amplifiers. The main aim of the proposed tool is to speed up the design process of RF
power amplifiers. In addition, it provides accurate final designs taking into consideration the effect of
parasitic components of both active and passive devices. The proposed tool relies on the knowledge
of designing highly linear RF power amplifiers. Both the optimization steps and design methodology
are presented in this paper. The proposed tool is verified by designing a highly linear RF power
amplifier at three different frequencies (7 GHz, 10 GHz, and 13 GHz) using 65 nm technology node.
The results show that an OP1 dB higher than 18 dBm, gain/S21 higher than 7 dB, and OIP3 higher
than 24 dBm at 6 dB back-off power can be obtained.
Keywords: automation; optimization; power amplifiers; linearization; efficiency; trade-offs; RF
1. Introduction
Today, for any wireless transceiver, the RF power amplifier (PA) is considered one
of the important building blocks. This is because RF power amplifiers determine the
maximum transmitted power. Designing CMOS RF power amplifiers is challenging due to
Citation: Onsy, R.A.; El-Nozahi, M.; several factors: First, the different performance specifications of a power amplifier, such
Ragai, H. Design-Aware as Gain, output 1 dB compression point (OP1 dB), efficiency, and output linearity are
Parasitic-Aware Simulation Based
dependable on each other. Second, those performance specifications are limited by the
Automation and Optimization of
existing layout parasitic components of both active and passive devices. Finally, it takes
Highly Linear RF CMOS Power
several, time consuming design iterations to account for the electromagnetic interaction
Amplifiers. Electronics 2023, 12, 272.
between the various passive components within the design [1–8].
https://doi.org/10.3390/
Design automation could help to reduce this design time and to reach an optimum
electronics12020272
design that meets the design targets [9,10]. However, the aforementioned challenges
Academic Editors: Rocco Giofre and present a limitation even if design automation is used. Design automation approaches that
Gaetano Palumbo overcome these challenges (trade-offs, effect of parasitic components, and electromagnetic
Received: 4 December 2022
interactions), while reducing time consuming electromagnetic (EM) simulations and layout
Revised: 29 December 2022 parasitic extraction, are required.
Accepted: 4 January 2023 The design automation of RF circuits, applied for the optimization of a low noise am-
Published: 5 January 2023 plifier (LNA), was introduced in [11] where a Pareto-optimal front (POF) of EM-simulated
inductors was obtained prior to the optimization. This approach is an offline design method-
ology where the inductor pareto-optimal fronts are independent of the circuit. Another
design automation approach, used for the optimization of a folded cascode operational
Copyright: © 2023 by the authors. transconductance amplifier (OTA), was presented in [12], where a simulation-based circuit
Licensee MDPI, Basel, Switzerland. sizing tool with a template-based layout generation tool were shown. The simulated-
This article is an open access article annealing-based optimization of a class C CMOS RF power amplifier (operating at a
distributed under the terms and frequency of 900 MHz) was introduced in [13]. The effect of the inductors was taken in
conditions of the Creative Commons
consideration by introducing a compact model including some of the parasitic compo-
Attribution (CC BY) license (https://
nents of the inductor. However, simulated-annealing optimization has slow convergence
creativecommons.org/licenses/by/
rates. A simulation-based optimization of RF amplifiers (operating at frequencies less
4.0/).
Electronics 2023, 12, 272. https://doi.org/10.3390/electronics12020272 https://www.mdpi.com/journal/electronicsElectronics 2023, 12, 272 2 of 17
than 10 GHz) was presented in [14], where an online inductor surrogate model was built
using machine learning techniques. The main challenge of this approach was that the
quality of the surrogate model is not always good, and it depends on the available training
data. Evolutionary algorithms were used in the optimization of an LNA in [15], but no
inductance modelling was included. Metaheuristics were used in the optimization of an
LC voltage-controlled oscillator (VCO) and a CMOS current feedback operational amplifier
(operating at a frequency of 1.5–2.5 GHz), using 2п inductance modelling [16]. Evolution-
ary algorithms were also used in the optimization of an operational amplifier (OPAMP)
and an LNA, where the inductance modelling was carried out using linear behavior into
performance models [17]. Evolutionary algorithms and simulated-annealing were used
in the optimization of single ended LNA and CMOS differential cross coupled oscillator
operating at 2.4 GHz frequency [18].
In this paper, a simulation based, design-aware, parasitic-aware optimization tool is
introduced for the design of highly linear RF CMOS power amplifiers. The introduced tool
overcomes the previously mentioned design challenges by integrating the design experience
within the optimization loop to speed up the design process. This design experience has to
be programmed once and can be used later for all other designs at different frequencies and
using different technology nodes. In addition, parasitic components are estimated such
that the outcome of the design tool is close to the final design. The proposed design-aware
tool does not require the design space exploration and/or the lengthy global optimization
algorithms that were presented in the previous publications [11,14–18]. The tool uses BFGS
optimization algorithm, implemented within the virtuoso environment [19], as the core
optimizer, and Spectre RF [20] as the simulation engine. The paper is organized as follows:
An overview of the proposed design tool and an illustration of the PA architecture adopted
in the tool are introduced in Section 2. Section 3 discusses the parasitic modelling approach
adapted within the tool. In Section 4, the details of the design-aware optimization and the
design flow are explained where the knowledge of the designer is integrated within the
tool. Test cases and the results of the optimization are shown in Section 5. A discussion is
found in Section 6. Finally, the paper is concluded in Section 7.
2. The Proposed Design Tool for RF Power Amplifiers
The core of the introduced design tool is made up of four main parts; the web interface,
the CAD RF circuit simulator, the Parasitic Model Generator, and the Optimizer. Figure 1
shows a simplified diagram of the core of the introduced design tool. The user enters the
required performance specifications of the RF power amplifier to the web interface. The
web interface is developed using PHP, HTML, CSS, and Java scripting. The communication
between the web interface and the RF circuit simulator (cadence-virtuoso) is established
through shell scripting and ocean scripting. The CAD RF Circuit Simulator (cadence-
virtuoso) is updated by the required performance specifications from the web interface.
Then, it invokes the cadence built-in optimizer, which updates the netlist of the adopted
highly linear RF power amplifier schematic. Multi-objective optimization is carried out
by the hybridization of design-aware optimization flow and the BFGS optimization algo-
rithm [21,22], which is employed in cadence built-in optimizer. The BFGS algorithm is used
for finding the best values of the design parameters that can meet the required constraints.
The parasitic models are priorly constructed within the parasitic model generator and
their values are updated by the optimizer. The new values are included in the updated
netlist. The optimization process continues till reaching the best achieved design point.
The resulting design parameters are then returned to the user along with the achieved
performance. The highly linear PA architecture, adopted as an application for the proposed
tool, is explained below.Electronics 2023, 12, x FOR PEER REVIEW 3 of 18
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of 18
17
Figure 1. The core of the design tool.
Figure 1. The core of the design tool.
The Adopted Highly Linear PA Architecture
The Adopted
The Adopted Highly Linear PA
PA Architecture
Figure 2a Highly
shows Linear
the highly Architecture
linear power efficient RF CMOS power amplifier archi-
Figure
Figure 2a
2a shows
shows the
the
tecture adopted by the introduced tool.highly
highly linear
Thepower
linear power efficient
architectureefficient RF RFCMOS
is based CMOS power
power
on achieving amplifier
amplifier
high architec-
linearity archi-
ture
bytectureadopted
using adopted by the introduced
by the introduced
parallel cascoded tool.
configuration The architecture
tool. The
(PCC)architecture is based
topologyisintroduced on achieving
based on achieving high linearity
2b by
high linearity
in [23]. Figure
using
by using
shows parallel
the PCC cascoded
parallel cascoded
amplifier configuration
configuration
topology (PCC) topology
(PCC)the
that improves topologyintroduced
linearity introducedin
of RF power[23]. Figure
in [23]. 2b shows
Figure
amplifiers 2b
the PCC amplifier
shows transconductance
through the PCC amplifiertopology that improves
topology that
linearization. the
Theimproves linearity
topologythe of RF
linearity
is made power
up of RF amplifiers
twopower through
amplifiers
parallel-con-
transconductance
nected cascode
through linearization.
branches.
transconductance The common The topology
linearization.sourceThe istopology
(CS) made up of
amplifier, two
is used
made parallel-connected
inuptheofmain
twobranch, cascode
is
parallel-con-
branches.
biased
nected The
to cascode common
operate as source
a class-AB
branches. Thepower(CS)
common amplifier,
amplifier used
sourcecarrying in the main
most ofused
(CS) amplifier, branch, is
the consumed biased
in the main to operate
current.
branch, is
as athe
while class-AB power
auxiliary amplifier
amplifier is carrying
biased to most ofasthe
operate a consumed
class B current.
amplifier. while the auxiliary
Transconductance
biased to operate as a class-AB power amplifier carrying most of the consumed current.
amplifier isis biased
linearization achieved to by
operate
choosing as atheclass B amplifier.
biasing voltages Transconductance
andBsizes linearization
and aux- is
of the Transconductance
main
while the auxiliary amplifier is biased to operate as a class amplifier.
achieved
iliary common by choosing
source the biasing
amplifiers suchvoltages
that and sizes of the of main and auxiliary arecommon
linearization is achieved by choosing thethe non-linearities
biasing voltages and both sizes branches
of the main par-aux-
and
source
tially amplifiers
cancelled such
outsource that
when amplifiers the non-linearities
added together. If thethe of both
biasing branches are
and sizingofofboth partially
bothbranches cancelled
branchesare out
arepar-
iliary common such that non-linearities
when
chosen added together. If the biasing and sizing of both branches are chosen such that the
tially such that the
cancelled outnth-order
when added transconductances
together. If theof the main
biasing andandsizingauxiliary
of bothamplifiers,
branches are
nth-order transconductances of the main and auxiliary amplifiers, G and G ,
Gn_main
chosenandsuch
Gn_auxiliary
that ,thehave almost similar
nth-order magnitudes and
transconductances of the 180main andn_main
degrees phase shift,
auxiliary n_auxiliary
their
amplifiers,
have
summation almost similar magnitudes and 180 degrees phase shift, their summation at the output
Gn_main andatGthe output
n_auxiliary node
, have resultssimilar
almost in theirmagnitudes
partial cancellation.
and 180 degrees phase shift, their
node results in their partial cancellation.
summation at the output node results in their partial cancellation.
(a)
Figure 2. Cont. (a)Electronics 2023, 12,
Electronics x FOR
2023, 12,PEER
272 REVIEW 4 of 18 4 of 17
(b)
Figure Figure
2. (a) Highly linear RF
2. (a) Highly power,
linear RF (b) the idea
power, of the
(b) the ideaadopted topology.
of the adopted topology.
Based on (1), on
Based (2),(1),
and(2),
(3),and
the(3),
partial cancellation
the partial of transconductance
cancellation non-linearities
of transconductance non-linearities
resultsresults
in the cancellation of third-order
in the cancellation and fifth-order
of third-order intermodulation
and fifth-order distortion
intermodulation (IMD3 (IMD3
distortion
and IMD5) as wellas
and IMD5) aswell
the cancellation of thirdoforder
as the cancellation thirdharmonic distortion
order harmonic (HD3) [23].
distortion (HD3) [23].
3 3_main + G3_auxiliary) + 25 A5 (G
iDS_3 = 3 A3 (G 255_main + G5_auxiliary),
(1)
iDS_3 = 4 A3 G3_main + G3_auxiliary 8 + A5 G5_main + G5_auxiliary , (1)
4 5 8
iDS_5 = A (G5_main + G5_auxiliary),
5 (2)
8
5 5
1 iDS_5 = A G5_main 25 + G5_auxiliary , (2)
iDS_3fo = A3 (G3_main + G3_auxiliary
8 )+ A5 (G5_main + G5_auxiliary), (3)
4 16
1 are 25
3 the third, fifth-order intermodulation
where iDS_3, iDS_5iDS_3fo
and iDS_3fo
= A G3_main + G3_auxiliary + A5 G5_main components (IMD3
+ G5_auxiliary , (3)
and IMD5) of drain current, 4 iDS, and third-order harmonic16distortion (HD3), respectively.
where iDS_3of, inon-linearities
The cancellation DS_5 and iDS_3foatare the third,
back-off powerfifth-order
results inintermodulation
better linearity components
and higher (IMD3
and
efficiency. IMD5) of drain current, iDS , and third-order harmonic distortion (HD3), respec-
Astively.
shown The cancellation
in Figure 2a, theofmainnon-linearities
and auxiliary at common
back-off source
power devices
results in better
have linearity and
separate
DC gatehigher efficiency.
biasing. This gives an extra degree of freedom in having different combinations
As shown
of biasing voltages andin sizes
Figure of 2a,
both thebranches
main and toauxiliary
achieve the common
requiredsource devices have
linearization. Theseparate
DC gate biasing.
input matching network This gives
used hasanaextraslightdegree of freedom
modification fromin having differentused
the commonly combinations
pi- of
biasing voltages and sizes of both
matching network, where C3 and C4 are added to be part ofbranches to achieve the required linearization.
input matching network The input
matching
to allow network
both branches to used
have ahas a slight
single input modification
matching network.from theThe commonly
Cascodedused pi-matching
configu-
network, where
ration is used to overcome C and C
3 breakdown4 are added to be part of the input matching
voltage limitations of CMOS devices. The differ- network to allow both
branches to have
ential configuration a single
reduces input matching
the bond-wire effect network. The Cascoded
of source grounding [23] configuration
and even-order is used to
overcome breakdown
intermodulation voltage limitations
distortion components (e.g., IMD2 of CMOS devices.
and IMD4). The differential
Stability is maintained configuration
in
reduces
the circuit the bond-wire
by using effect ofloops
negative feedback source madegrounding [23] RC
up of series andnetworks.
even-order intermodulation
These nega-
distortion
tive feedback loopcomponents
components (e.g.,
areIMD2 and IMD4).
optimized Stability
to maintain is maintained
stability without in the circuit
causing a se-by using
negative feedback loops made up of series RC networks.
vere gain decrease. C7 and C8 are placed at the gates of the cascode devices of both the These negative feedback loop
components are optimized to maintain stability without
main and auxiliary amplifiers and optimized to maintain equal VDS swings across the com- causing a severe gain decrease.
C7 andand
mon source C8 the
are common
placed atgate the gates
devices of of
theeach
cascodebranchdevices
despiteof both the main
any change in and
inputauxiliary
power.amplifiers
The output and optimized
matching to maintain
networks equal VDSnetworks
are pi-matching swings across
wherethe common source and
a center-tapped
the common
inductance is used as gate devices
shown of each
in Figure 2a.branch despite any change in input power. The output
matching networks are pi-matching networks where a center-tapped inductance is used as
shown in Figure 2a.before and after post layout simulations.
3.1. Parasitic Modelling for Passive Devices
Electronics 2023, 12, 272 The inductances and capacitances used in the optimization process are 5 of 17the foun
process design kit (PDK) devices, their corresponding parasitic components are inclu
within the design kit models. The optimization of the physical parameters of passive
3. Parasitic Modelling
vices is carried out. The physical parameters of the inductance that are to be optim
Including
are the inner the layout
radius parasitic
and the number components
of turns,inwhile
the design
thoseprocess
of thesaves a lot of time
capacitance are the len
and effort. It results in accurate designs whose performance specifications are the same
andbefore
width.and after post layout simulations.
3.2. 3.1. Parasitic
Parasitic Modelling for
Modelling forPassive
ActiveDevices
Devices
The inductances and capacitances used in the optimization process are the foundry
The modelling of the parasitic capacitances arising from transistor layout and it
process design kit (PDK) devices, their corresponding parasitic components are included
terconnects
within thewhen
designoperating
kit models. at gigahertz
The frequencies
optimization is carried
of the physical out and
parameters included in
of passive
schematic tocarried
devices is be taken
out. in
Theconsideration during
physical parameters optimization.
of the inductance that are to be optimized
are the inner
Figure radius and
3 shows thethe number of turns, MOSFET
parasitic-aware while thosemodel
of the capacitance are the
used within length
the proposed
and width.
Using S-parameter simulations of the parasitic extracted view of the PDK transistor ta
in consideration parasitic
3.2. Parasitic Modelling components
for Active Devices arising from its interconnects, the impedance
ues seenThe from its three
modelling terminals
of the parasitic are plotted with
capacitances arisingrespect to frequency.
from transistor Thus,
layout and its the ex
capacitances
interconnects ofwhen
Cgs, operating
Cgd, andat Cds resulting
gigahertz fromisthe
frequencies layout
carried are included
out and estimated. These va
in the
schematic to be taken in consideration during optimization.
are calculated at different values of channel width. Figure 4 shows the excess capacita
Figure 3 shows the parasitic-aware MOSFET model used within the proposed tool.
of Cgs, Cgd, and Cds versus the width of the transistor. As depicted, as the width o
Using S-parameter simulations of the parasitic extracted view of the PDK transistor taking
transistor increases,
in consideration those
parasitic capacitances
components arisingincrease linearly. Polynomial
from its interconnects, the impedanceexpressions
values of
parasitic capacitances
seen from as functions
its three terminals of the
are plotted number
with respectoftofingers of the
frequency. transistor
Thus, the excess are obta
capacitances
using least-mean of Cgs, Cgd, and
squares Cds resulting
curve-fitting from the Equations
method. layout are estimated. These values
(4)–(6) show the resulting
are calculated at different values of channel width. Figure 4 shows the excess
pressions of the parasitic capacitances after taking the number of multipliers (M) of t capacitances
of Cgs, Cgd, and Cds versus the width of the transistor. As depicted, as the width of the
sistor in consideration.
transistor increases, those capacitances increase linearly. Polynomial expressions of the
parasitic capacitances as functions of the number of fingers of the transistor are obtained
Cgs (in fF) = (1.1 N + 1.5) ∗ M
using least-mean squares curve-fitting method. Equations (4)–(6) show the resulting
expressions of the parasitic capacitances after taking the number of multipliers (M) of
transistor in consideration. Cgd (in fF) = (1.1 N + 0.4) ∗ M
CgsC(in
ds (in
fF) =fF)
(1.1= N + 1.5)N∗+M1.69) ∗ M
(1.59 (4)
Cgd (in and
where N is the number of fingers fF) = M
(1.1isNthe
+ 0.4) ∗M
number (5)
of multipliers of transistors.
Cds (in fF) = (1.59 N + 1.69) ∗ M
finger width is fixed to 2 µ m. (6)
where N is the number of fingers and M is the number of multipliers of transistors. The
finger width is fixed to 2 µm.
Figure 3. Parasitic-aware transistor model.
Figure 3. Parasitic-aware transistor model.Electronics
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FOR PEER REVIEW 6 of 1817
6 of
Cgs
Cgd
Cds
Figure 4. Cgs, Cgd, and Cds versus the number of fingers of RF transistor (N).
Figure 4. Cgs, Cgd, and Cds versus the number of fingers of RF transistor (N).
4. Design- Aware Optimization and the Proposed Design Flow
4.4.1.
Design-
DesignAware Optimization
Trade-Offs and Analysis
and Sensitivity the Proposed Design Flow
4.1. Design Trade-Offs
The key component and Sensitivity Analysis design-aware optimization is to combine the
of the proposed
knowledge
The keyofcomponent
the designer of along with the optimization.
the proposed design-aware For the power is
optimization amplifier shown
to combine thein
Figure 2a, almost
knowledge all the design
of the designer alongparameters are affecting all
with the optimization. Forthetheperformance
power amplifierspecifications.
shown
inThose
Figure specifications
2a, almost all include the output
the design 1 dB compression
parameters are affecting point (OP1
all the dB), Gain, output
performance third
specifica-
order intercept point (OIP3) at the operating power, power added
tions. Those specifications include the output 1 dB compression point (OP1 dB), Gain, efficiency (PAE), and
input/output matching. The sensitivity of each performance specification
output third order intercept point (OIP3) at the operating power, power added efficiency to each design
parameter
(PAE), (width, biasing,
and input/output capacitances,
matching. and inductances)
The sensitivity is different. For
of each performance the proposed
specification to
each design parameter (width, biasing, capacitances, and inductances) is different. For theto
design-aware optimization, those sensitivities are identified and taken in consideration
speed updesign-aware
proposed the design time. Trade-offs are
optimization, thosealso understoodare
sensitivities from this sensitivity
identified and taken test.
in con-
sideration to speed up the design time. Trade-offs are also understood from this sensitiv-to
Below, some examples showing the sensitivity of the performance specifications
the
ity various design parameters are discussed and verified with simulations. Table 1 lists
test.
typical values
Below, someof the design parameters
examples showing thethat are used of
sensitivity forthe
theperformance
sensitivity analysis/simulation.
specifications to
Figure 5a shows the simulation results of the OIP3 versus the output power for different
the various design parameters are discussed and verified with simulations. Table 1 lists
channel widths of the transistors of the main and auxiliary amplifiers. As depicted, the
typical values of the design parameters that are used for the sensitivity analysis/simula-
OIP3 depends significantly on the width of the channel of both the main and auxiliary
tion. Figure 5a shows the simulation results of the OIP3 versus the output power for dif-
branches. This is because the OIP3 relies on the non-linearities cancellation between these
ferent channel widths of the transistors of the main and auxiliary amplifiers. As depicted,
two branches.
the OIP3 depends significantly on the width of the channel of both the main and auxiliary
branches. This isofbecause
Table 1. Values the OIP3
all the design relies on
parameters the non-linearities
in Figure 2a. cancellation between these
two branches.
Design Parameters Design Values
Table 1. Values
Length of all of all the design parameters in Figure 2a.
transistors 60 nm
Width of M1 and M3 100 µm
Design Parameters Design Values
Width of M2 and M4 300 µm
Length of all transistors 60 nm
Vm (Main) 370 mv
Width of M1 and M3 Va (auxiliary)
100 µ m 370 mv
Biasing
Width of M2 and M4 Vcas (cascode) 300 µ m 1.55 v
Vm (Main)Lin 370 mv 430 pH
Biasing Va (auxiliary)
C1 370 mv 700 fF
Input Matching Network C2
Vcas (cascode) 1.55 v 250 fF
Lin C3 , C4 430 pH 1 pF
C1 Cout 700 fF 400 fF
Input Matching Network
Output Matching Network C2 Lout 250 fF 850 pH
C3, C4 L_CT 1 pF 1 nH
Cout R 400 fF 2 kΩ
Feedback Stability Loops
C 100 fF
Output Matching Network Lout 850 pH
Gate Capacitances L_CT C7 1 nH 365 fF
C8 365 fF
Feedback Stability Loops R 2 kΩC 100 fF
C7 365 fF
Electronics 2023, 12, 272 Gate Capacitances 7 of 17
C8 365 fF
(a) (b)
Figure 5. (a)
Figure OIP3
5. (a) versus
OIP3 versusPout,
Pout,(b)
(b) power addedefficiency
power added efficiency (PAE)
(PAE) versus
versus Pout
Pout for different
for different sizes sizes
of of
main and auxiliary amplifiers.
main and auxiliary amplifiers.
It isIt important
is importantto to note
note that
that thehighest
the highestOIP3
OIP3values
values are
are achieved
achieved when
whenbothbothsizes
sizes are
are equal to 300 µm, yet the corresponding PAE is the worst as shown
equal to 300 µ m, yet the corresponding PAE is the worst as shown in Figure 5b. The in Figure 5b. The best
best efficiency is achieved when both transistors have sizes equal to 100 µm, while the
efficiency is achieved when both transistors have sizes equal to 100 µ m, while the OIP3
OIP3 shows a peaking around 10 dBm. The dependency of OP1 dB on the width of the
shows a peaking around 10 dBm. The dependency of OP1 dB on the width of the channel
channel is shown in Figure 6, and as expected the larger the width, the higher the achieved
is shown
OP1 dB.inThose Figure 6, and asindicate
simulations expectedthatthe
thelarger
channel the width,
width the the
of both higher
mainthe andachieved
auxiliary OP1
Electronics 2023, 12, x FOR PEER REVIEW
dB.branches
Those simulations
determine theindicate
OIP3, OP1 that
dB, the
and channel
efficiency.width
There isofalso
both the main
a tradeoff and those
between 8 of 18
auxiliary
branches
performancedetermine the OIP3,
parameters OP1and
(efficiency dB,OP1
anddB/OIP3).
efficiency. There
Thus, is also
reaching the arequired
tradeoff between
design
those performance
targets parameters
could be time consuming (efficiency
task. and OP1 dB/OIP3). Thus, reaching the required
design targets could be time consuming task.
Figure 7 shows the dependency of OIP3 on the biasing voltages of both main and
auxiliary amplifiers. As shown, OIP3 at backed off power increases with increasing the
biasing voltage of one of the two amplifiers. However, the best efficiency, as shown in
Figure 8, is achieved when Vm = Va = 370 mv which corresponds to an OIP3 peaking
around 10 dBm output power (as shown in Figure 7). Thus, from Figures 7 and 8, it is
noted that the best non-linearities cancellation provided by the architecture is achieved
for this design when Vm = Va = 370 mv. The OP1 dB is determined by the biasing voltage
of the main amplifier, as shown in Figure 9. From Figures 5−9, it is indicated that the chan-
nel widths of the transistors and their biasing affect the OP1 dB, OIP3, and efficiency, and
there is an optimum set of design parameters that leads to the optimum solution to satisfy
the design requirements. The dependence of OP1 dB on the values of the output matching
network is simulated in Figures 10 and 11. As expected, the output matching network
affects significantly the OP1 dB. This is because the values of those passive components
determine the optimum impedance for power matching.
Figure 6. OP1 dB versus channel widths of main and auxiliary amplifiers.
Figure 6.Figure
OP1 dB versus the
7 shows channel widths ofofmain
dependency OIP3and
on auxiliary amplifiers.
the biasing voltages of both main and
auxiliary amplifiers. As shown, OIP3 at backed off power increases with increasing the
biasing voltage of one of the two amplifiers. However, the best efficiency, as shown in
Figure 8, is achieved when Vm = Va = 370 mv which corresponds to an OIP3 peaking
around 10 dBm output power (as shown in Figure 7). Thus, from Figures 7 and 8, it is noted
that the best non-linearities cancellation provided by the architecture is achieved for this
design when Vm = Va = 370 mv. The OP1 dB is determined by the biasing voltage of the
main amplifier, as shown in Figure 9. From Figures 5–9, it is indicated that the channelElectronics 2023, 12, 272 8 of 17
widths of the transistors and their biasing affect the OP1 dB, OIP3, and efficiency, and there
is an optimum set of design parameters that leads to the optimum solution to satisfy the
design
Figure requirements.
6. OP1 The dependence
dB versus channel of OP1
widths of main anddBauxiliary
on the values of the output matching
amplifiers.
network is simulated in Figures 10 and 11. As expected, the output matching network
affects significantly the OP1 dB. This is because the values of those passive components
Figure 6. OP1 dB versus channel widths of main and auxiliary amplifiers.
determine the optimum impedance for power matching.
Figure 7. OIP3 versus Pout for different biasing voltages of main and auxiliary amplifiers.
Figure 7. OIP3 versus Pout for different biasing voltages of main and auxiliary amplifiers.
Figure 7. OIP3 versus Pout for different biasing voltages of main and auxiliary amplifiers.
Electronics 2023, 12, x FOR PEER REVIEW 9 of 18
Figure 8. PAE versus Pout for different biasing voltages of main and auxiliary amplifiers.
Figure 8. PAE versus Pout for different biasing voltages of main and auxiliary amplifiers.
Figure 8. PAE versus Pout for different biasing voltages of main and auxiliary amplifiers.
Figure
Figure9.9.OP1
OP1dB
dBversus biasingvoltages
versus biasing voltagesofof main
main andand auxiliary
auxiliary amplifiers.
amplifiers.Electronics 2023, 12, 272 Figure 9. OP1 dB versus biasing voltages of main and auxiliary amplifiers. 9 of 17
Figure 9. OP1 dB versus biasing voltages of main and auxiliary amplifiers.
Figure 10.10.
Figure OP1 dBdBversus
OP1 versuscenter-tapped outputinductance.
center-tapped output inductance.
Figure 10. OP1 dB versus center-tapped output inductance.
0-5 5-10
10-15
0-5 15-20
5-10
10-15 15-20
Figure 11. OP1 dB versus Cout and Lout, at L_CT = 700 pH.
Figure 11. OP1 dB versus Cout and Lout, at L_CT = 700 pH.
Figures 12 and 13 show the changes in OP1 dB and S21 versus the value of the cascode
Figure 11. OP1 dB
gate capacitor, versus
Cgate. As Cout and Lout,
depicted, at L_CT
the value = 700
of Cgate pH. the OP1 dB. This is because the
affects
Figures
voltage 12 and
swings 13drain
at the show of the changesdevices
the cascode in OP1 aredB and S21
divided versus
equally the value
between of the cas-
the voltages
code gate
across capacitor,
Figures
the drain andCgate.
12 and 13 show
source As depicted,
the changes
terminals the
of the value
inmain
OP1and dBofcascode
Cgate
and S21affects
versusthe
transistors OP1
theusing
valuedB.ofThis
Cgate. is
the cas-
because the
However,
code voltage swings
the gain is reduced
gate capacitor, at
Cgate. as the
Asthe drain of the
value of this
depicted, cascode
the capacitance devices
value of Cgatedecreasesare divided
(another
affects equally
trade-off).
the OP1 be-
dB. This is
Electronics 2023, 12, x FOR PEER REVIEW
tween the
Figures voltages
14 and 15 across
show the
the drain
effect of and source
changing terminals
cascode gate of the
biasing main
voltage and
on cascode
OP1 dB 10 of 18
transis-
and
because the voltage swings at the drain of the cascode devices are divided equally be-
OIP3.
tors using
tween Both
the OP1 However,
Cgate.
voltages dB across
and OIP3 theare
the affected
gain
drain is because
reduced
and sourceas they
thedepend
value
terminals onthis
ofof
the the non-linear
capacitance
main output
and cascode decreases
transis-
impedance
(another of the main
trade-off). device.
Figures 14 and 15 show the effect of changing cascode gate biasing
tors using Cgate. However, the gain is reduced as the value of this capacitance decreases
voltage on trade-off).
(another OP1 dB and OIP3. Both
Figures 14 andOP115dB andthe
show OIP3 are affected
effect because
of changing they gate
cascode depend on
biasing
the non-linear
voltage output
on OP1 impedance
dB and OIP3. Bothof the
OP1main device.
dB and OIP3 are affected because they depend on
the non-linear output impedance of the mainindevice.
The sensitivity analysis is summarized Table 2, which shows the performance
specifications and their
The sensitivity corresponding
analysis design parameters
is summarized in Table 2, to which
which they the
shows are most sensi-
performance
tive. Based on the above sensitivity analysis and the understanding of the trade-offs
specifications and their corresponding design parameters to which they are most sensi- be-
tween the performance
tive. Based specifications,
on the above the proposed
sensitivity analysis design-aware
and the optimization
understanding is created.
of the trade-offs be-
tween the performance specifications, the proposed design-aware optimization is created.
Figure 12. OP1 dB versus Cgate.
Figure 12. OP1 dB versus Cgate.Figure 12. OP1 dB versus Cgate.
Electronics 2023, 12, 272 10 of 17
Figure 12. OP1 dB versus Cgate.
Figure 13. S21 versus frequency at different values of Cgate.
Figure 13. S21 versus frequency at different values of Cgate.
Figure 13. S21 versus frequency at different values of Cgate.
Electronics 2023, 12, x FOR PEER REVIEW 11 of 18
Figure 14. OP1 dB versus cascode gate biasing voltage.
Figure 14. OP1 dB versus cascode gate biasing voltage.
Figure 14. OP1 dB versus cascode gate biasing voltage.
Figure 15. OIP3 versus Pout at different values of cascode gate biasing voltage.
Figure 15. OIP3 versus Pout at different values of cascode gate biasing voltage.
The sensitivity analysis is summarized in Table 2, which shows the performance
specifications and their
Table 2. Performance corresponding
specifications design
and their parameters todesign
corresponding whichparameters.
they are most sensitive.
Based on the above sensitivity analysis and the understanding of the trade-offs between
Performance Specifications
the performance Designdesign-aware
specifications, the proposed Parametersoptimization is created.
Cout, Lout, and L_CT
OP1 dB
Wm, Wa, Vm, Va, and Cgate
OIP3 Vm, Va, Wm, and Wa
Cout, Lout, and L_CT
Gain (S21) Lin, C1, C2, C3, and C4
Wm, Wa, Vm, Va, and CgateElectronics 2023, 12, 272 11 of 17
Table 2. Performance specifications and their corresponding design parameters.
Performance Specifications Design Parameters
Cout, Lout, and L_CT
OP1 dB
Wm, Wa, Vm, Va, and Cgate
OIP3 Vm, Va, Wm, and Wa
Cout, Lout, and L_CT
Gain (S21) Lin, C1, C2, C3, and C4
Wm, Wa, Vm, Va, and Cgate
Wm and Wa
PAE
Vm and Va
4.2. The Optimization Flow
The proposed optimization flow used within the tool is presented in Figure 16. The
optimization engine uses the BFGS optimization algorithm implemented within the virtu-
oso environment. The flow relies on five main steps. Below is the explanation of each step
and how it is integrated within the tool:
1. The user enters the frequency of operation and the required specifications (minimum
OP1 dB, minimum OIP3 at 6 dB back off power, minimum OIP3 at 10 dB back-off
power and minimum gain (S21)) to the tool web interface. The minimum value of
OIP3 at 6/10 dB back-off power will determine the efficiency of the power amplifier.
In addition, weights for each targeted design specification are defined.
2. The stability of the amplifier is considered as a hard constraint that needs to be met
regardless of the performance specifications.
3. The initial values of the design parameters need to be defined at the beginning of the
optimization. Table 1 shows typical values for those parameters.
4. Step 1 in Figure 16: the optimization of the input matching network parameters
(C1 , C2 , C3 , C4 , and Lin) is carried out. The input to this step is the frequency and
performance specifications entered by the user. The optimized values are input to
steps 2, 3, 4, and 5.
5. Step 2 in Figure 16: the optimization of the output matching network parameters (Cout,
Lout, and L_CT) is carried out. The input to this step is the frequency, performance
specifications entered by the user, and the optimized parameters from step 1. The
optimized values are input to steps 3, 4, and 5.
6. Step 3 in Figure 16: the optimization of the biasing and sizing of transistors (Vm, Va,
Wm, and Wa) is carried out. The input to this step is the frequency, performance
specifications entered by the user, and the optimized parameters from steps 1 and 2.
At the end of this step, the modelled parasitic capacitances arising from the transistor
layout and its interconnects (Cgs, Cgd, and Cds) are updated corresponding to the
optimized widths of the transistors (Wm and Wa). The optimized values are input to
steps 4 and 5.
7. Step 4 in Figure 16: the optimization of the gate capacitance (C7 and C8 ) and the
cascode gate DC biasing voltage (Vcas) are carried out. The input to this step is
the frequency, performance specifications entered by the user, and the optimized
parameters from steps 1, 2, and 3. The optimized values are input to step 5.
8. Step 5 in Figure 16: it is considered an evaluation point, which determines the next
step in the optimization flow.
9. If all the specifications (OP1 dB, S21, and OIP3) or (OP1 dB and S21) or (OIP3 and S21)
or S21 failed, then the optimization flow is directed to step 1, where the values of the
input matching network parameters are being optimized again, then all the rest of the
steps will follow in succession. It is to be noted that when step 1 is carried out this
time, all the other design parameters have new optimized values that differ from their
previous values when step 1 was visited for the first time.Electronics 2023, 12, 272 12 of 17
10. If (OP1 dB and OIP3) or OP1 dB failed, then the optimization flow is directed to step 2,
then all the rest of the steps (3, 4, and 5) will follow.
11. If OIP3 failed, the optimization flow is directed to step 3, and then steps 4 and 5
will follow.
12. The optimization flow stops when the best achieved design point is obtained based
on the pre-defined weighting factors.
13. The tool will return back to the web interface: the achieved values for all the required
performance specifications, the consumed DC power, PAE at OP1 dB and at 6 dB
Electronics 2023, 12, x FOR PEER REVIEW back-off power, the values of the optimized design parameters, the circuit 13 of 18
schematic,
a template of the layout of the circuit, and a GDSII file for further modifications.
Figure 16.
Figure 16. The
The proposed
proposedoptimization
optimizationflow.
flow.
5.5. Automation
Automation and
and Test
Test Cases
CasesResults
Results
The proposed
The proposed design
designtooltoolofofthe
thepower
poweramplifier
amplifier is is
used
used forfor
automatic
automaticsizing. Three
sizing. Three
test cases are applied at three different frequencies (7, 10, 13 GHz). The 65
test cases are applied at three different frequencies (7, 10, 13 GHz). The 65 nm technology nm technology
node is
node is used
usedforforthese testtest
these cases. Initially,
cases. the user
Initially, thespecifies the required
user specifies performance
the required spec-
performance
ifications: frequency of operation, OP1 dB, Gain, and OIP3 at 6 dB
specifications: frequency of operation, OP1 dB, Gain, and OIP3 at 6 dB back off and back off and 10 dB back
10 dB
off power to the web interface. Weights for different performance
back off power to the web interface. Weights for different performance specifications specifications are also are
defined
also by the
defined byuser. At the
the user. Atend
theofendtheof
automatic sizing,sizing,
the automatic values values
of the different design pa-
of the different design
parameters, as well as the achieved performance specifications, are displayedoutput.
rameters, as well as the achieved performance specifications, are displayed as A A
as output.
GDSII layout template for the adopted architecture is also
GDSII layout template for the adopted architecture is also generated. generated.
Figures 17−21 show the achieved Pout, OIP3, PAE, AM-AM, and AM-PM distortions
and S21 for the three different frequencies (7,10, and 13 GHz). The targeted OP1 dB is
higher than 18 dBm, gain is higher than 7 dB, OIP3 is higher than 24 dBm at 6 dB back-off
power. As depicted from Figures 17−21, the targeted performance specifications are
achieved. Table 3 show the required and achieved performance specifications. Finally,
Figure 22 shows the layout template of the amplifier which is provided by the proposedElectronics 2023, 12, 272 13 of 17
Figures 17–21 show the achieved Pout, OIP3, PAE, AM-AM, and AM-PM distortions
and S21 for the three different frequencies (7,10, and 13 GHz). The targeted OP1 dB 14
Electronics 2023, 12, x FOR PEER REVIEW is of 18
higher than 18 dBm, gain is higher than 7 dB, OIP3 is higher than 24 dBm at 6 dB back-
Electronics 2023, 12, x FOR PEER REVIEW 14 of 18
off power. As depicted from Figures 17–21, the targeted performance specifications are
achieved. Table 3 show the required and achieved performance specifications. Finally,
Electronics 2023, 12, x FOR PEER REVIEW 14 of 18
Figure 22 shows the layout template of the amplifier which is provided by the proposed
design automation tool. A computer with an Intel core i7 processor with 12 GB RAM is
used to run this tool.
Figure 17. Pout versus Pin at the three test cases.
Figure 17. Pout versus Pin at the three test cases.
Figure 17. Pout versus Pin at the three test cases.
Figure 17. Pout versus Pin at the three test cases.
Figure 18. OIP3 versus Pout at the three test cases.
Figure 18. OIP3 versus Pout at the three test cases.
Figure 18. OIP3 versus Pout at the three test cases.
Figure 18. OIP3 versus Pout at the three test cases.
Figure 19. PAE versus Pout at the three test cases.
Figure 19. PAE versus Pout at the three test cases.
Figure 19. PAE versus Pout at the three test cases.
Figure 19. PAE versus Pout at the three test cases.Electronics 2023, 12, x FOR PEER REVIEW 15 of 18
Electronics 2023,2023,
Electronics 12, x12,
FOR272PEER REVIEW 15 of 18
14 of 17
Figure 20. AM-AM and AM-PM distortion versus Pout at the three test cases.
Figure 20. AM-AM and AM-PM distortion versus Pout at the three test cases.
Figure 20. AM-AM and AM-PM distortion versus Pout at the three test cases.
Figure 20. AM-AM and AM-PM distortion versus Pout at the three test cases.
Figure
Figure 21.21.
S21S21 versus
versus frequency
frequency at the
at the three testthree
cases. test cases.
Figure 21. S21 versus frequency at the three test cases.
Figure 21. S21 versus frequency at the three test cases.
Figure 22. Layout of the power amplifier.
Figure
Figure 22.22. Layout
Layout of theofpower
the power amplifier.
amplifier.
Figure 22. Layout of the power amplifier.Electronics 2023, 12, 272 15 of 17
Table 3. The required and achieved performance specifications.
Achieved
Performance Specifications Required
7 GHz 10 GHz 13 GHz
OP1 dB >18 dBm 19 dBm 18.2 dBm 18.1 dBm
OIP3 at 6 dB back-off power >24 dBm 26 dBm 25.2 dBm 24.7 dBm
S21 >7 dB 8.7 dB 7.1 dB 7.3 dB
DC Consumed Power - 89.5 mw 89.52 mw 55 mw
PAE at OP1 dB - 27% 22 % 29%
PAE at 6 dB back-off - 22% 9% 15%
6. Discussion
The four main aspects that are used in the comparison of the different approaches of RF
design optimization and automation are: performance evaluators, inductance modelling,
included layout parasitic components and the used optimizers. Table 4 shows a summary
of the recent approaches in the sizing and optimization of RF circuits [9].
Table 4. Summary of the recent approaches in the sizing and optimization of RF circuits.
Layout Included Parasitic
Work Performance Evaluator Inductor Modelling Optimizer
Components
Circuit Simulator and Evolutionary
[15], 2000 Not Included Device and interconnect C and CC
Performance Models Algorithms
Parasitic-included
[13], 2001 Parametric Equations Not Included Simulated-Annealing based
compact model
[24], 2002 Circuit Simulator In-the-loop EM simulation Not Included Simulated-Annealing based
[25], 2004 Performance Models Linear behavior into PMs Not specified Simulation-based
EM-based surrogate
[14], 2012 Circuit Simulator Not Included Evolutionary Algorithms
model built in the loop
Evolutionary Algorithms and
[18], 2016 Circuit Simulator 2-п model Other passive components
simulated-Annealing
EM-Simulated
Particle Swarm Optimization
[11], 2017 Circuit Simulator Pareto-Optimal Front Not Included
(PSO)
(POF) obtained a priori
Device and interconnect C, CC,
[17], 2017 Performance Models Linear behavior into PMs Evolutionary Algorithm based
and R
[16], 2022 Circuit Simulator 2-п model Not Included Meta-heuristics algorithms
Foundry process design
This Work Circuit Simulator Device and interconnect C and CC BFGS algorithm
kit (PDK) model
The performance evaluation is carried out either by using performance models, para-
metric equations, or circuit simulators. Performance models are inaccurate and must be
varied with the variation of circuit topologies [9]. Circuit simulators are the most accurate
performance evaluators.
The inductance modelling differs from one approach to another, as shown in Table 4. In
the proposed tool, the inductance used is the foundry process design kit (PDK) inductance,
modelling the inductance layout parasitic components with high accuracy. Using the PDK
inductance model allows the optimization of the physical parameters of the inductance,
such as the inner radius and the number of turns to reach the required performance
specifications. This results in good estimation of the results of post layout simulations.
Including layout parasitic components in the optimization process differs from one
approach to another, as shown in Table 4. In the proposed tool, the post layout simulations
of the parasitic extracted view of the transistor along with its interconnects was carried outElectronics 2023, 12, 272 16 of 17
prior to the optimization process and the resulting parasitic capacitances were included in
the optimization process as functions of the sizes of the transistors.
The optimization process differs according to the optimization algorithm used as
shown in Table 4. The proposed tool uses BFGS optimizer that is employed by cadence-
virtuoso. The BFGS optimizer is used to select the best values of the design parameters that
can achieve the required specifications.
7. Conclusions
A parasitic-design-aware simulation-based design tool was proposed for highly linear
RF power amplifiers within this paper. Both the optimization steps and design method-
ology were explained and they rely on the knowledge of the circuit to obtain the design
parameters. The proposed tool does not need lengthy simulations when compared to the
existing approaches. With parasitic modelling, the design point is close to the final design
after layout. The proposed tool was verified to design a highly linear RF power amplifier
at three different frequencies (7 GHz, 10 GHz, and 13 GHz) using 65 nm technology node.
The results showed that an OP1 dB higher than 18 dBm, gain/S21 higher than 7 dB, and
OIP3 higher than 24 dBm at 6 dB back-off power are obtained.
Author Contributions: Conceptualization, R.A.O. and M.E.-N.; formal analysis, R.A.O.; investigation,
R.A.O.; methodology, R.A.O.; supervision, M.E.-N. and H.R.; validation, R.A.O.; visualization, R.A.O.;
writing—original draft, R.A.O.; writing—review and editing, M.E.-N. All authors have read and
agreed to the published version of the manuscript.
Funding: This research received no external funding.
Data Availability Statement: Some of the data presented in this study are available upon request
from the corresponding author.
Acknowledgments: The authors would like to thank engineer Ahmed Samir for his remarkable help
with the software part of the web tool.
Conflicts of Interest: The authors declare no conflict of interests.
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