ASCLIN Asynchronous Synchronous Interface - AURIX Microcontroller Training V1.0 2019-03 - Infineon Technologies
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ASCLIN
Asynchronous Synchronous Interface
AURIX™ Microcontroller Training
V1.0 2019-03
Please read the Important Notice and Warnings at the end of this documentASCLIN
Asynchronous Synchronous Interface
ATX Pin Highlights
x.y
ARX LIN
Pin
x.y
Provide asynchronous serial communication
ARTS
Port Control with external devices using only data-in,
ACTS SPI
ASCLIN (Master) data-out signals. The focus of the module is
ASCLKO set to fast and flexible communication: either
ASC fast point-to-point or master-to-many slaves
ASLSO
Pin communication using the LIN protocol
x.y
Key Features Customer Benefits
3 in 1 module Customer can use single module for ASC
(UART), LIN and Master SPI applications
Configurable oversampling per bit Choose up to 16 oversampling per bit for
higher accuracy for higher baud rates
2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 2ASCLIN
3 in 1 Module
ASCLKO
ARX
ATX
ASCLIN
ASLSO
ARTS
ACTS
› ASCLIN module supports three different serial protocol standards:
ASC(UART)
LIN
SPI
› Customer can leverage three protocols support without additional hardware
› SPI master is supported with three or four wire approach (with or without slave select
output signal)
2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 3ASCLIN
Configurable oversampling per bit
› Programmable oversampling of 4 Open
Microcontroller 1 drain Microcontroller 2
to 16 times per Bit as shown in bus
a) b) c)
figure waveform ASC TX ASC RX
› Programmable sample point 10 11 12 10 11 12
position with respect to the a) Waveform at
oversampling points in the range of the transmitting
module output
0 to 15
› Programmable number of samples b) Waveform on
the open-drain
per bit between 1 or 3 bus
c) Waveform at
the receiving
module input
d) Oversampling of the
receiving module waveform
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
1 bit 1 bit
2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 4ASCLIN
System integration
› ASCLIN module is integrated to
fASCLINS
provide following benefits: fASCLINF
ARX
Interrupts signals capable of fERAY
fOSC0 ATX
triggering either CPU or DMA Pin
Internal loop-back mode for
CLOCK
CONTROL
PORT CONTROL
test functionality ARTS
Up to 4 ASCLIN channels SPB ASCLIN
ACTS Pin
available with flexible
connections to multiple GPIO
ASCLKO
via multiplexers for
ASLSO
transmission and reception Pin
CPUx
RXSR
respectively IR TXSR
EXSR
DMA
2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 5Application example
LIN
ATX
LIN
ARX
Overview Advantages
› Supports all four elementary LIN › Auto baud detection
transactions including header/response
transmission & reception, as master or › Optional collision detection
slave › Bus idle monitoring and wake-up
› Supports standard v1.3/2.0/2.1 and capabilities
J2602 with collision detection › Stuck at zero/one monitoring for safety
2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 6Application example
ASC
ATX
ATX ARX
High-
Standard
Speed
ASC ARX ARTS
ASC
ACTS
Overview Advantages
› Configure UART communications › Extended supports of different sensors
through high-speed ASC extension
› Support UART standard JASO D 903
› Extension in functionality to support
› Supports baudrates up to 25 MBaud optional handshaking (RTS/CTS) for
high-speed ASC communication
2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 7Application example
SPI master
SCLKO ASCLKO
SCLKO
ARX ARX
(MRST) ARX Half- (MRST)
4-Wire 3-Wire
(MRST) Duplex
SPI ATS SPI ATS
(MTSR) ATS SPI (MTSR)
ASLSO (MTSR) ASLSO
Overview Advantages
› SPI master configuration for SPI based › Up to 16 bit data width supported
communications in multiple
configurations › Programmable leading & trailing delays
› Support of full and half duplex
› Supports baudrates up to 25 MBaud
2019-03-27 Copyright © Infineon Technologies AG 2019. All rights reserved. 8Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2019-03 IMPORTANT NOTICE For further information on the product,
Published by The information given in this document shall in no technology, delivery terms and conditions and
Infineon Technologies AG event be regarded as a guarantee of conditions or prices please contact your nearest Infineon
81726 Munich, Germany characteristics (“Beschaffenheitsgarantie”) . Technologies office (www.infineon.com).
With respect to any examples, hints or any typical
© 2019 Infineon Technologies AG. WARNINGS
values stated herein and/or any information
All Rights Reserved. Due to technical requirements products may
regarding the application of the product, Infineon
contain dangerous substances. For information
Technologies hereby disclaims any and all
Do you have a question about this on the types in question please contact your
warranties and liabilities of any kind, including
document? nearest Infineon Technologies office.
without limitation warranties of non-infringement
Email: erratum@infineon.com
of intellectual property rights of any third party. Except as otherwise explicitly approved by
Infineon Technologies in a written document
Document reference In addition, any information given in this
signed by authorized representatives of Infineon
AURIX_Training_1_ document is subject to customer’s compliance
Technologies, Infineon Technologies’ products
Asynchronous_Synchronous_Interface with its obligations stated in this document and
may not be used in any applications where a
any applicable legal requirements, norms and
failure of the product or any consequences of the
standards concerning customer’s products and
use thereof can reasonably be expected to result
any use of the product of Infineon Technologies in
in personal injury.
customer’s applications.
The data contained in this document is exclusively
intended for technically trained staff. It is the
responsibility of customer’s technical
departments to evaluate the suitability of the
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