ULTRA LOW POWER AND LOW COST ASYNCHRONOUS SERVICE NETWORK ARCHITECTURE FOR ADAPTIVE BLOCKS RECONFIGURATION IN AN IOT WIRELESS SENSOR NODE CIRCUIT ...
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Ultra Low Power and low cost
Asynchronous Service Network
Architecture for Adaptive Blocks
Reconfiguration in an IoT
Wireless Sensor Node Circuit
ASYNC 2016
www.cea.fr
Chairat Soundous, Edith Beigné, Ivan Miro-Panades,
Florent Berthier, Marc Belleville
&
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titre
§ 30 to 50 billions of smart-objects by 2020 (The Economist & BI)
§ Many applications to address new challenges
§ 70 % of the World’s population in cities by 2050 Æ smart-building & transport
§ 33 % of the World’s population over 65 years old by 2050 Æ smart-health
§ Why low-power ?
§ Global Energy Impact
§ Convenience (all-day battery life)
§ Small form factor (in-body implants)
§ Maintenance-free (wide deployment)
May 2016
& © CEA. All rights reserved DACLE Division| January 2013
Sept 2014 |2
Adaptativity
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pour modifier Energy in WSN
style du titre
Low power in WSN is an important system
requirement
Adaptativity in WSN for low energy
Tracking the Optimum Energy Point
Adaptativity to on-going application requirements
Adaptativity to on-going environment
Adaptive blocks control IP1
Adaptive blocks: System
WSN are mixed-signal!
Actuators
targets
§ Analog Freq Vdd Vbp IP2
Control
§ DigitalS1 Sensors
Control
Adaptive blocks
IP control
S2
§ Consumption constraints
S3Speed constraints
§ Latency and IPn
Different latency, power and
data bandwidth constrains What interconnection network ?
fusion
& © CEA. All rights reserved May
Sept2016
DACLE Division| January 2013
2014 |3SoA:pour
Cliquez usualmodifier
communication
le stylenetworks
du titre
Frame
Bus Topology Arbitration
Data_bus Address_bus
PLB Hierarchical bus 32/64/128/256 32 Priority
CoreConne
OPB Hierarchical bus 32 32 Priority
ct
DCR Daisy chain 32 10 Priority
Application
AHB Hierarchical bus 32/64/128/256 32
AMBA
dependent
APB Hierarchical bus 32/64/128/256 32 X
AMBA (ARM)
Frame adapted for large data
CoreConnect:
DCR: used for configuration purposes
Can only reconfigure digital blocks
Problem: networks designed for multi-core communication
• Too high of a throughput
& • DCR is oversized need May
DACLE Division| January
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Sept2016
2014SoA : dedicated
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MNoC (Monitoring Network on Chip)
Packetization of data into flits => routing thanks to LUTs =>
depacketisation
Use of 2 channels: priority and normal channel
CHAIN
Delay insensitive Network on Chip
Use of narrow signalling channels
High speed operation links
[3]http://apt.cs.manchester.ac.uk/projects/interconnect/
Problem: these networks are used for servicing multi-core chips, to bypass
latency problems, or to target specific applications [2]Madduri,S. DATE 2009
& © CEA. All rights reserved May
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DACLE Division| January 2013
2014 |5Service Network
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le style du titre
In
Microcontroller Configuration manager
Out
Configuration
Adaptive
SIC
blocks
Data
Adaptive
SIC
blocks
Adaptive
blocks
May2016
& © CEA. All rights reserved DACLE Division| January 2013
Sept 2014 |6Fresh Ideas
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pour evolution
modifier for IoT
le style duWSN
titre
In
Microcontroller Configuration manager
Out
Digital
0101011010
adaptive SIC
blocks
Data
Analog
adaptive SIC
blocks
May 2016
& © CEA. All rights reserved DACLE Division| January 2013
Sept 2014 |7Firstpour
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Asynchronous QDI logic Network
Robustness Serial Interface Controller
Quick wake up Interface
Event driven circuit
Adaptive Adaptive
Block1 Block2
Data_cfg_in BLOC_in
BP_BLOC_out
Interface Interface
BLOC_out
0.5 pJ/bit 0.7 pJ/bit
SIC fjb
1.2 ns/bit 2 ns/bit
BP_BLOC_out
Adaptive Adaptive
Block4 Block3
BP_BLOC_out
Data_cfg_out Interface
BP_BLOC_out Interface
BLOC_out BLOC_out BLOC_out
0.25 pJ/bit 1 pJ/bit
1.2 pJ/bit 2.8ns/bit
1ns/bit 3.3ns/bit
& © CEA. All rights reserved May
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DACLE Division| January 2013
2014 |8Conclusion
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Conclusion
Reconfiguration network for adaptive blocks in a WSN node circuit
§ Not only for digital blocks (usual) but also for analog blocks
Asynchronous logic implementation
Low cost and low energy network
Reconfiguration of Frequency Locked Loop as example
Perspectives
Digital configuration hardware implementation and fabrication
Analog Block reconfiguration mechanisms
& © CEA. All rights reserved May
Sept2016
DACLE Division| January 2013
2014 |9Thank you
Centre de Grenoble Centre de Saclay
soundous.chairat@cea.fr
contact.dacle@cea.fr
17 rue des Martyrs
38054 Grenoble Cedex
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