Trabajo Fin de Grado/Máster - CEI-UPM
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Código F2021_1 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
DC Transformer based on DC-DC converter
Summary
The goal of this project is to find a solution for an efficient and light
energy processing DC-DC converter for future weight-critical transport
applications. This will be achieved by the means of a novel and optimized
Air Core Solid State Transformer (SST).
SST is a component which has been the key enabler of DC power grid
paradigm, as it integrates energy conversion and galvanic isolation into a
single device. In conservative designs, the galvanic isolation is obtained
through a bulky low frequency transformer made of iron and copper and
this project will develop a novel solution, a novel energy processing
component, that omits employment of such an element as magnetic core,
consequently decreasing the weight of transport vehicles (airplanes,
ships, trains), and its CO2 footprint.
The student will have to analyze different possible topological solutions,
research the impact of the latest semiconductor technology (SiC and GaN)
and perform a theoretical design of the described DC-DC converter.
Advisor(s): Miroslav Vasić
Contact email: miroslav.vasic@upm.es
UD Ingeniería Electrónica
Curso 2020/21
Código F2021_2 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado
Characterization of a SiC Power Module
Summary
SiC has revolutionized Power Electronics, especially in
the field of renewable energies, pushing the design
envelope beyond the unimaginable limits.
In this Project it is necessary to characterize a SiC module
in different operating conditions. It will be necessary to
model the device, design an experimental setup and
perform experiments in order to clearly identify possible
applications where this module could be applied.
Advisor(s): Miroslav Vasić
Contact email: miroslav.vasic@upm.es
UD Ingeniería Electrónica
Curso 2020/21
Código F2021_3 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Fast and efficient Power Converters based on GaN
Summary
The issue of low consumption for autonomous and mobile
devices (mobile phones, tablets, communication nodes ...) is
of the outmost importance. Most of these devices have an
RF amplifier that means high energy consumption. One of
the modern techniques to lower its consumption is to feed it
with a variable voltage depending on the signal it amplifies.
In this project the student will use the latest semiconductor
technology based on GaN. These transistors allow us to use
frequencies in the MHz range implemented ultra efficient
and ultra compact power supplies.
The objective is to design a source and verify its operation.
Advisor(s): Miroslav Vasić
Contact email: miroslav.vasic@upm.es
UD Ingeniería Electrónica
Curso 2020/21
Código F2021_4 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado
IEEE International Future Energy Challenge
Summary
Para la aplicaciones de automoción el rendimiento y
densidad de potencia de los convertidores de potencia son
los parámetros más importantes del diseño.
En este proyecto es necesario diseñar un convertidor
continua-continua de 1500 W de potencia de salida, con
rendimiento por encima de 96% y densidad de potencia de
20kW/dm3.
Para ello se va a apostar por la tecnología de
semiconductores basados en GaN y magnéticos integrados.
El alumno tendrá que realizar un diseño avanzado de los
componentes magnéticos basados en la PCB optimizando lo
desde el punto de vista de tamaño y pérdidas.
Advisor(s): Miroslav Vasić
Contact email: miroslav.vasic@upm.es
UD Ingeniería Electrónica
Curso 2020/21
Código F2021_5 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Advanced Modelling of the latest Silicon IGBT
Summary
Technology revolution in Power Electronics started with SiC
and GaN that have outperformed well established Si devices.
Nevertheless, the silicon-based solutions will outperform the
future SiC and GaN designs for many more years in the terms
of cost-to-performance-ratio which is the main driver for
great number of cost sensitive industrial applications.
This activity is under the umbrella of an international
consortium lead by Infineon and Fagor, among the others.
The goal of this project is to model the latest Infineon Si
IGBTs, verify the models through a set of experiments and
clearly identify possible applications where this device will
bring better performance than SiC MOSFET and to prove it
through different design cases.
Advisor(s): Miroslav Vasić
Contact email: miroslav.vasic@upm.es
UD Ingeniería Electrónica
Curso 2020/21
Código F2021_6 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Analysis and design of DC microgrids for more electric transportation
Summary
To reduce emissions and decrease fuel consumption, the
goal for future transportation is to replace most of the major
systems currently utilizing nonelectric power, such as
environmental controls and engine start, with new electrical
systems to improve efficiency, emissions, reliability, and
maintenance costs. To do that, a DC microgrid is needed to
distribute the power to the different subsystems .
The goal of this work is to analyze the stability of DC
microgrid with DC-DC transformers for transportation
applications.
Required skills: Fundamentos de Automática, Electrónica de
Potencia.
Advisor(s): Regina Ramos / Miroslav Vasić
Contact email: regina.ramos@upm.es
UD Ingeniería Electrónica
Curso 2020/21
Código F2021_7 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Design and validation of DC transformers for electrical vehicles
Summary
DC transformers are very useful in the emerging
battery driven DC world. They allows cell balancing
for solar cells and most any kind of electrochemical
cells. In electrical vehicles, DC motors, of any
voltage, can be driven from DC cells of any voltage,
with only a DC Transformer interface. A DC
transformer is generated by adding a number of
overdriven mosfets to an AC Transformer.
The goal of this work is to obtain a set of rules to
optimize the volume and efficiency of DC
transformers.
Required skills: Fundamentos de Automática,
Electrónica de Potencia.
Advisor(s): Regina Ramos / Miroslav Vasić
Contact email: regina.ramos@upm.es
UD Ingeniería Electrónica
Curso 2020/21
Código F2021_8 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Design of prototype for brain tumor therapy validation
Summary
Glioblastoma (GBM) is the most frequent and devastating
primary brain tumor. Recently, a new therapy based on the
application of electric fields has been approved.
This project envisages to develop a prototype of an
implantable device which will be capable of generating the
electric fields required to stop the reproduction of cancer
cells.
This project is in collaboration with the National Cancer
Research Center (CNIO) and the Neurosurgery Service of
Hospital de la Princesa.
Required skills: Power electronics, Motivation
Software: Pspice, LTspice, Altium
Advisor(s): Regina Ramos / Miguel Jiménez Carrizosa
Contact email: regina.ramos@upm.es
miguel.jimenezcarrizosa@upm.es
UD Ingeniería Electrónica
Curso 2020/21
Código F2021_9 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Electromagnetic analysis of an implanted antenna in the brain
Summary
New treatments in neurosurgery involve the implantation of
tiny devices, which are capable of treating certain types of
neurological diseases.
The report of internal measurements to external equipment is
a key factor for correct follow-up of the patient's state and
treatment.
This project envisages to design, analyze and verify the
communication module of the implanted device.
This project is in collaboration with the Neurosurgery Service
of Hospital de la Princesa.
Required skills: Basic digital system design, Motivation
Advisor(s): Jorge Portilla / Miguel Jiménez Carrizosa
Contact email: jorge.portilla@upm.es
miguel.jimenezcarrizosa@upm.es
UD Ingeniería Electrónica
Curso 2020/21
Código F2021_10 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Design and implementation of a circuit with ARM Cortex-A7 microprocessor and
Coral TPU for Deep Neural Networks processing
Summary
Deep learning has gained attraction in the last years
due to its good performance in image processing.
There is a tendency to bring resources to the edge,
close to data source. In this context, it becomes
more and more important to process data locally,
which impose huge challenges in architectures and
algorithms, due to resources limitations.
In this project the idea is to create a processing
circuit board for LIDAR point cloud processing using
neural accelerators, in the context of edge
computing.
Advisor(s): Jorge Portilla
Contact email: jorge.portilla@upm.es
UD Ingeniería Electrónica
Curso 2020/21Código F2021_11 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Generation of 3D environments with Unity for LG simulator for auto-labeled
dataset generation with LIDAR
Summary
Data set availability is crucial in Deep neural
networks training.
The use of simulators for LIDARs in realistic
environment can help in this issue, by generating
datasets on demand and moreover, and very
important, allowing automatic labeling.
In this project, the idea is to be able to generate 3D
environments on demand for LIDAR simulation and
generation of datasets on demand for Deep learning
training.
Advisor(s): Jorge Portilla
Contact email: jorge.portilla@upm.es
UD Ingeniería Electrónica
Curso 2020/21Código F2021_12 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Análisis e implementación de un sistema de detección de acoplamiento virtual
en trenes, basado en tecnología Ultra-Wideband (UWB)
Summary
La rápida evolución de las tecnologías de comunicaciones y
procesamiento embebido dentro del paradigma de Internet de las
Cosas (en inglés Internet of Things, IoT) están posibilitando la
promoción de novedosos sistemas que monitorización, control y
gestión automática en diversos ámbitos de aplicación, como es el
caso del entorno ferroviario. En tal sentido, uno de los principales
temas de interés es el denominado Virtual Coupling o acoplamiento
virtual, que tiene como objetivo incrementar y optimizar de forma
segura la capacidad y circulación de la infraestructura ferroviaria con
estrategias de detección automática entre trenes adyacentes.
Este trabajo tiene como objetivo el estudio e implementación de un
sistema de medición y detección entre trenes mediante tecnología
inalámbrica UWB, dentro del marco de un proyecto europeo de
investigación en el ámbito ferroviario.
Advisor(s): Gabriel Mujica
Contact email: gabriel.mujica@upm.es
UD Ingeniería Electrónica
Curso 2020/21Código F2021_13 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Máster
Optimización de técnicas de comunicación multi-salto en redes sensores
inalámbricas para Internet de las Cosas
Summary
El paradigma de Internet de las Cosas (en inglés Internet of Things, IoT)
engloba la integración de diversas tecnologías hardware, software y de
comunicación inalámbricas para posibilitar la interacción entre
dispositivos heterogéneos distribuidos en diversos ámbitos de aplicación,
como las Smart Cities, sistemas inteligentes de transporte e Industria 4.0.
Uno de los aspectos fundamentales del funcionamiento de estas redes
inalámbricas y en particular del despliegue de nodos sensores en dichos
entornos reales de aplicación es la implementación de estrategias de
encaminamiento multi-salto y adaptación de topologías de red dinámica,
para así conseguir una comunicación e intercambio de datos de forma
remota y fiable entre los extremos de la red.
En este trabajo se propone el análisis y optimización de algoritmos de
encaminamiento dinámicos basados en tecnología hardware/software de Cookie Node
IoT, para así posibilitar el despliegue y adaptación automática de redes
de sensores inalámbricas en entornos de aplicación cambiantes.
Advisor(s): Gabriel Mujica
Contact email: gabriel.mujica@upm.es
UD Ingeniería Electrónica
Curso 2020/21Código F2021_14 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Implementación de estrategias de Computation Offloading en redes de sensores
inalámbricas de bajo consumo para Internet de las Cosas
Summary
El paradigma de Internet de las Cosas (en inglés Internet of Things, IoT)
engloba la integración de diversas tecnologías hardware, software y de
comunicación inalámbricas para posibilitar la interacción entre dispositivos
heterogéneos distribuidos en diversos ámbitos de aplicación, como las Smart
Cities, sistemas inteligentes de transporte e Industria 4.0. Las redes de
sensores inalámbricas se caracterizan por una limitada capacidad en
términos de ancho de banda, consumo energético y recursos de
procesamiento, con el fin de posibilitar un tiempo de vida mucho mas
prolongado y totalmente desatendido de la red.
En tal sentido, en este trabajo se propone el análisis y optimización de
algoritmos de Computation Offloading sobre tecnología hardware/software
de IoT para obtener un balance entre modos automáticos de operación con
consumo reducido de los nodos sensores, optimización de la trasmisión y
procesamiento de datos entre los dispositivos participantes de la red, y la
carga computacional tanto individual como colaborativa entre los mismos.
Advisor(s): Gabriel Mujica
Contact email: gabriel.mujica@upm.es
UD Ingeniería Electrónica
Curso 2020/21Código F2021_15 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Máster
Deep Neuroevolution in Reconfigurable Hardware
Summary
This project aims at developing a neuro-evolvable
hardware architecture capable of lifelong learning in
dynamic environments. The hardware architecture
will be based on a modular implementation of
SqueezeNet, which is a highly efficient Convolutional
Neural Network topology, specially designed for
embedded domains. Together with the network, an
evolutionary algorithm will be also implemented as
the optimization algorithm in charge of training of
the network, as an alternative to traditional
backpropagation methods.
Advisor(s): Andrés Otero
Contact email: joseandres.otero@upm.es
UD Ingeniería Electrónica
Curso 2020/21Código F2021_16 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Máster
Hardware-based Neuroevolution with Indirect Encoding
Summary
This project aims at developing a neuro-evolvable hardware
architecture for dynamic system’s control.
The hardware architecture will be a highly regular computing
substrate implemented on an FPGA, which configuration is indirectly
encoded. This indirect encoding is evolved by a second evolutionary
network, which provides the potential configurations. This learning
strategy increases the potential of the network to discover solutions
to given problems.
Required skills: digital system design in RTL using HDLs (VHDL and/or
Verilog), System-on-Chip Programming.
Advisor(s): Andrés Otero
Contact email: joseandres.otero@upm.es
UD Ingeniería Electrónica
Curso 2020/21Código F2021_17 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Máster
Feature Extraction for Physiological Signal Processing using Genetic
Programming
Summary
Genetic programming is a type of Evolutionary Algorithm (EA),
which aims at automatically creating a computer program from a
description of goals, without being explicitly programmed for it.
In this project, we will apply Genetic Programming techniques to
autonomously “discover” new features from a benchmark of
physiological signals, which can be used in the Machine Learning
Domain for an effective detection of anomalies. Matlab will be used
during the first stages of the work, and the best solution will be
potentially implemented in a FPGA.
Required skills: digital system design in RTL using HDLs (VHDL
and/or Verilog), System-on-Chip Programming.
Advisor(s): Andrés Otero
Contact email: joseandres.otero@upm.es
UD Ingeniería Electrónica
Curso 2020/21Código F2021_18 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Design and implementation of a Delineation accelerator for e-Health Machine
Learning systems
Summary
e-Health is a new trend whose objective is to improve the
patient diagnosis incorporating his/her daily life state into the
analysis. Wearable devices with the power of Machine Learning
techniques offer the possibility of measuring the physiological
condition during daily activities, creating a “real-world” scenario
for e-Health applications.
The goal of this project is to develop a hardware accelerators for
extracting bioparameters of a photoplethysmogram to aid e-
Health Machine Learning systems.
Required skills: digital system design in RTL using HDLs (VHDL
and/or Verilog).
Advisor(s): Andrés Otero / Rodrigo Mariño
Contact email: joseandres.otero@upm.es
UD Ingeniería Electrónica
Curso 2020/21Código F2021_19 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Máster
Advanced Reconfigurable Multi-Accelerator Systems with Xilinx Dynamic
Function eXchange
Summary
This project aims at exploring and evaluating the possibilities of the
novel design flow for dynamic reconfigurable systems, proposed by
Xilinx, and known as “Dynamic Function eXchange”. A system with
multiple reconfigurable accelerators will be implemented using this
flow, to explore its main benefits and drawbacks. Some criteria such
as flexibility, productivity and modularity will be evaluated.
Required skills: digital system design in RTL using HDLs (VHDL and/or
Verilog), System-on-Chip Programming, Reconfigurable Computing.
More information about Xilinx Dynamic Function eXchange:
https://www.xilinx.com/support/documentation-navigation/design-
hubs/dh0017-vivado-partial-reconfiguration-hub.html
Advisor(s): Andrés Otero / Alfonso Rodríguez
Contact email: joseandres.otero@upm.es
UD Ingeniería Electrónica
Curso 2020/21Código F2021_20 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Máster
Hardware/Software Co-Simulation of SoPCs using QEMU
Summary
Quick EMUlator (QEMU) is a generic and open-source machine &
userspace emulator and virtualizer. It can emulate a complete
machine (i.e., computer architecture) in software without any need
for hardware virtualization support. Hence, it allows developers to
run and test ARM or RISC-V application binaries on their workstations
rather than on the target embedded platforms.
While QEMU can be used to evaluate the software components of a
System on Programmable Chip (SoPC), it is still difficult to simulate
hardware components and, more specifically, the hardware/software
interactions. This project aims at developing a co-simulation
environment for hardware-accelerated applications running under
Linux, connecting HDL and SystemC modules with QEMU.
Required skills: digital system design using both HDLs (VHDL and/or More information about Xilinx QEMU:
Verilog) and SystemC, software programming in C, Linux. https://www.xilinx.com/support/documentation/s
w_manuals/xilinx2020_2/ug1169-xilinx-qemu.pdf
Advisor(s): Alfonso Rodríguez / Andrés Otero
Contact email: alfonso.rodriguezm@upm.es
UD Ingeniería Electrónica
Curso 2020/21Código F2021_21 Carga lectiva 12 ECTS Fecha Febrero 2021
Trabajo Fin de Grado/Máster
Automated Test Infrastructure for Reconfigurable Multi-Accelerator Systems
Summary
ARTICo³ is an open-source run-time reconfigurable processing
architecture to enable hardware-accelerated high-performance
embedded computing. It comes with an automated toolchain that takes
either low-level HDL code (VHDL/Verilog) or high-level C/C++ code (using
an HLS engine) and generates reconfigurable hardware accelerators.
Currently, ARTICo³ does not provide any means to validate hardware-
accelerated functionality before it is implemented on the FPGA (e.g., RTL
simulation is not supported), nor does it provide any run-time hardware
debugging mechanism. The goal of this project is to develop an
automated test infrastructure to address these issues.
Required skills: digital system design in RTL using HDLs (VHDL and/or
Verilog), System-on-Chip integration, software programming in C.
Advisor(s): Alfonso Rodríguez
Contact email: alfonso.rodriguezm@upm.es
UD Ingeniería Electrónica
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