Report of Contributions - AMICSA 2014 - Fifth International Workshop on Analogue and Mixed-Signal Integrated Circuits for Space Applications ...
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AMICSA 2014 - Fifth
International Workshop on
Analogue and Mixed-Signal
Integrated Circuits for Space
Applications
Report of Contributions
https://indico.cern.ch/e/AMICSA2014AMICSA 2014 - F … / Report of Contributions Creating and Updating Standards f …
Contribution ID: 1 Type: Oral
Creating and Updating Standards for New Analog
and Mixed-Signal ICs for Space Missions
Monday, 30 June 2014 09:50 (20 minutes)
On December 20, 2013, the Defense Logistics Agency (DLA) released revision K of microcircuit
specification, MIL-PRF-38535. This document revision is significant because it updates existing
requirements and creates requirements for new analog and mixed-signal integrated circuits (ICs)
including those that are built as flip-chips and with columns attached. It also introduces and en-
ables Class Y, a new category of microcircuits for space. Development of Class Y was a NASA-led
initiative for the space community to infuse new technology into military/space standards. With
the availability of analog-to-digital (A/D) and digital-to-analog (D/A) converters operating in giga-
hertz (GHz) frequencies, the screening and qualification of such microcircuits is being reviewed by
the industry and government users with the goal of clarifying and adding to the existing require-
ments. Lastly, a summary will be given of radiation characteristics of analog ICs. These single
event and total dose radiation characteristics will be presented at the next Nuclear and Space Ra-
diation Effects Conference (NSREC).
Primary author: Mr AGARWAL, Shri (NASA/JPL-CalTech)
Presenter: Mr AGARWAL, Shri (NASA/JPL-CalTech)
Session Classification: Need and Requirements for Radiation Hardened Analogue and Mixed-
Signal ICs
Track Classification: AMICSA 2014
July 5, 2022 Page 1AMICSA 2014 - F … / Report of Contributions Rad-hard High Speed LVDS Driver …
Contribution ID: 2 Type: Oral
Rad-hard High Speed LVDS Driver and Receiver
Tuesday, 1 July 2014 12:10 (20 minutes)
A big challenge in data transmission is the constant increase in data-rate. Low Voltage Differ-
ential Signaling (LVDS) is a high speed, low power general purpose standard interface. Our pa-
per presents LVDS driver and receiver circuits specifically designed, packaged and qualified for
use in aerospace environment. The intended application of these devices (RHFLVDS31/32 quad
drivers/receivers) is point to point baseband data transmission over controlled impedance media
with 100 Ω characteristic impedance.
A LVDS Driver and a LVDS Receiver have been processed in a 0.13um CMOS STMicroelectronics
technology. The Driver accepts low voltage TTL input levels and translates them to low voltage
(350mV) differential output signals. The Receiver accepts low voltage (100mV) differential LVDS
input signals and translates them to TTL output levels. It can operate over a large common mode
input range from -4V to +5V, using a new architecture, to ensure immunity of ground shifting and
driver offset voltage, while supply voltage can vary from 3 to 3.6V. To this purpose, the common
voltage input is sensed and adjusted to a fixed reference voltage 1.5V with an integrator loop and a
class AB transconductor. These devices support data rates of 400 Mbps or equivalently a 200 MHz
signal.
These two LVDS circuits are designed for space applications. A total ionizing dose test campaign
on elementary components has been performed to investigate the technology radiation hardness.
The components have been radiated at high dose rate using a C060 gamma ray source. Specific
mitigation techniques to achieve best in class hardness to total ionization dose and heavy ions have
been applied. Moreover, the chosen technology has a substrate with very low resistivity which is
very useful to decrease risks of latch up in general and more specifically Single Event Latch up.
One major challenge of these LVDS circuits has been to meet particular ESD specifications which
were 16kV on LVDS receiver input and driver output combined with SEL immunity. Laser tests
have been useful to best understand their behavior regarding latch up.
Both the Receiver and Driver have been evaluated in laboratory. Huge efforts and specific equip-
ment have been necessary to measure properly propagation delays close to 1.7ns with good accu-
racy (better than 100ps). Finally, 300 krad in high dose rate and 150krad in low dose rate radiation
tests have been performed successfully. Heavy ion Single Events Effects tests have also been per-
formed with good results.
Primary authors: Mrs MORCHE, Colette (STMicroelectronics); Mrs NICOLAS, Sandrine (STMi-
croelectronics); Mr MASSON, Thierry (STMicroelectronics)
Co-author: Mr JIMENEZ, Jean (STMicroelectronics)
Presenter: Mr MASSON, Thierry (STMicroelectronics)
Session Classification: Applications for Radiation Hardened Analogue and Mixed-Signal
ASICs
Track Classification: AMICSA 2014
July 5, 2022 Page 2AMICSA 2014 - F … / Report of Contributions SEE Characterization of a Magnet …
Contribution ID: 3 Type: Oral
SEE Characterization of a Magnetometer Front-End
ASIC using a RHBD Digital Library in AMS 0.35um
CMOS
Monday, 30 June 2014 11:50 (20 minutes)
A radiation-hardened-by-design (RHBD) digital library, developed for the Austria Microsystems
(AMS) 0.35um CMOS technology has been applied in a mixed-signal ASIC that operates as a multi-
channel data acquisition system for magnetometers using anisotropic magneto-resistances (AMR).
The circuit has been tested in the Heavy-Ion facilities of the Université Catholique de Louvain-
la-Neuve (HIF-UCL). The experimental results demonstrate a LET threshold of 22.5 MeV·cm2/mg
and absence of latchup up to 81.8 MeV·cm2/mg. SEE performance of the A/D converters has also
been measured. This radiation-tolerant performance is obtained at the cost of a penalty in area
and power with respect to the unhardened technology.
Primary authors: Mr ARIAS-DRAKE, Alberto (Dpto. de Electrónica y Electromagnetismo, U.
de Sevilla); Mr RAMOS-MARTOS, Juan (Instituto de Microelectrónica de Sevilla); Mr CARRANZA-
-GONZÁLEZ, Luis (Dpto. de Electrónica y Electromagnetismo, U. de Sevilla); Mr SORDO-IBAÑEZ,
Samuel (Dpto. de Eelctrónica y Electromagnetismo, U. de Sevilla)
Co-authors: Mr RAGEL-MORALES, Antonio (Instituto de Microelectrónica de Sevilla); Mrs PIÑERO--
GARCÍA, Blanca (Dpto. de Electrónica y Electromagnetismo, U. de Sevilla); Mr CEBALLOS-CÁCERES,
Joaquín (Instituto de Microelectrónica de Sevilla); Mr MORA-GUTIÉRREZ, José Miguel (Instituto de
Microelectrónica de Sevilla); Mr MUÑOZ-DÍAZ, Manuel (Dpto. de Electrónica y Electromagnetismo,
U. de Sevilla); Mr LAGOS-FLORIDO, Miguel Ángel (Instituto de Microelectrónica de Sevilla); Dr ESPE-
JO-MEANA, Servando (Dpto. de Electrónica y Electromagnetismo, U. de Sevilla)
Presenter: Mr RAMOS-MARTOS, Juan (Instituto de Microelectrónica de Sevilla)
Session Classification: Radiation Hardened Technology for Mixed-Signal IC
Track Classification: AMICSA 2014
July 5, 2022 Page 3AMICSA 2014 - F … / Report of Contributions NEW ID MOS PDK for SPACE AP …
Contribution ID: 4 Type: Oral
NEW ID MOS PDK for SPACE APPLICATIONS
Monday, 30 June 2014 14:00 (20 minutes)
Two years ago, ID MOS had the first demand to develop mixed-signal ASIC for Space applications.
After having a look to the existing PDKs, we discovered that there was still no full Space PDK
available, especially with regard to device models. ID MOS decided to develop its own PDK, for
the low space voltage applications. This PDK had to provide hardened components to reach the
specified radiation tolerance (TID : 100krad, SEL : LET 80,72Mev.cm²/mg). To reach this target we,
first, chose a technology, developed our own test chip including different modules based on new
ELT transistor drawings, fabricate the circuit, define the assembly and the electrical test. Then for
the NEOSAT project, we received the same demand for High Voltage circuits. We chose the same
technology XH035 from XFAB complemented with different modules allowing the integration of
High Voltage ELT transistors (up to 90V).
We propose to present for the radiation hardened XH035 technology the baseline technology test
chips and radiation test results. Finally the current state of the ID MOS solution is presented for
Space mixed Analog/Digital ASICs, based on the XFAB XH035µm technology.
Primary author: Mr LATIMIER, Paul-Emile (ID MOS)
Presenter: Mr LATIMIER, Paul-Emile (ID MOS)
Session Classification: Radiation Hardened Technology for Mixed-Signal IC
Track Classification: AMICSA 2014
July 5, 2022 Page 4AMICSA 2014 - F … / Report of Contributions A radiation-hardened and low flic …
Contribution ID: 5 Type: Oral
A radiation-hardened and low flicker noise ASIC
preamplifier designed in CMOS technology for the
ultra-sensitive ESA JUICE search coil magnetometer
Monday, 30 June 2014 11:10 (20 minutes)
Important space scientific missions such as ESA CLUSTER (2000), NASA THEMIS (2007), NASA
MMS (2014), ESA/JAXA BepiColombo (2016) and ESA JUICE (2024) have and will incorporate an
ultra-sensitive three-axis Search Coil Magnetometer (SCM) to measure the magnetic field vector.
Over the years, the instrument, which is designed by the LPP/CNRS, has become a reliable and
essential device due to the in situ demonstrated performances in terms of high magnetic reso-
lution, robustness, low power consumption and its ease of implementation. The SCM operates
in low-frequencies from 0.1 Hz to a few dozen kHz. Therefore, in order to achieve a femtoTesla
(fT/sqrt(Hz)) sensitivity (noise floor), the equivalent input noise of the readout electronics must be
lower than some nV/sqrt(Hz). Here, we are particularly confronted to the flicker noise (1/f). The
electronics’ power consumption is to be considered during the design flow since this is a crucial
aspect in space applications, among other specifications, for the instrument’s lifetime. Further-
more, related effects to cumulative radiation dose, heavy ions and temperature should not impact
the readout electronics specifications and therefore the SCM sensitivity.
In this paper, we will introduce the principle of the designed SCM for JUICE (JUpiter ICy moons
Explorer) which operates in the frequency range 0.1 Hz – 20 kHz. The SCM should provide a 4 fT
@5kHz sensitivity (noise floor). The mission’s environment requires an operating temperature of
-150 ℃ and a total ionizing dose of 300 krads (under shielding).
To meet those constraints, an application-specification-integrated-circuit (ASIC) designed in 0.35µm
CMOS technology is proposed. It consists of a low flicker noise preamplifier. The interest in a
monolithic integration of the readout electronics is explained. An analytic study of MOSFET tran-
sistor noise contribution was done to allow the considerable reduction of the flicker noise (1/f)
and to achieve, thanks to an appropriate transistors dimensioning, an input equivalent noise of 4
nV/sqrt(Hz) and a current noise of 20 fA/ sqrt(Hz) at 10Hz. The chip was exposed to a 300 krads
of Colbalt-60 total ionizing dose (TID) and tested in nitrogen temperature (77 °K). Measured noise
and gain variations of the preamplifier do not affect the SCM sensitivity. The ASIC power con-
sumption is 16 mW, which is interesting if compared to previous adopted electronics based on
discreet components. The ASIC radiation-hardiness is insured by enclosed-gate layout transistors
and guard-rings around each device.
In the second section of the paper, we will discuss the new ASIC design, which will include, in
addition to the low noise preamplifier, a supply voltage regulator and a band-gap voltage reference.
The interest of those new functions is to improve the insensitivity of the supply voltage and the
biasing in a wide temperature range, which starts at 77°K.
Primary author: RHOUNI, Amine (Laboratory of Plasmas Physics (LPP/CNRS))
Co-authors: Dr COILLOT, Christophe (Laboratoire Charles Couloumb, CNRS); Dr SOU, Gerard
(Electronics and Electromagnetism Laboratory - UR2 (UPMC)); Dr MANSOUR, Malik (Laboratory of
Plasmas Physics (LPP/CNRS))
Presenter: RHOUNI, Amine (Laboratory of Plasmas Physics (LPP/CNRS))
July 5, 2022 Page 5AMICSA 2014 - F … / Report of Contributions A radiation-hardened and low flic … Session Classification: Applications for Radiation Hardened Analogue and Mixed-Signal ASICs Track Classification: AMICSA 2014 July 5, 2022 Page 6
AMICSA 2014 - F … / Report of Contributions Very High Resolution Analog-to- …
Contribution ID: 6 Type: Oral
Very High Resolution Analog-to-Digital Converter at
1 kHz for Space Applications
Tuesday, 1 July 2014 16:00 (20 minutes)
We present a monolithic, very high resolution analog-to-digital converter suitable for high preci-
sion space applications. The converter is a low-noise, low sampling rate, radiation hardened device
optimized to operate in a frequency range from 0.1mHz to 1kHz with nominal output sampling
frequency of 6 kHz. The ADC receives a differential voltage input and outputs 24-bit word samples.
A simple serial output interface is used. The converter operates on a single clock domain. System
architecture is based on a
2nd order, discrete-time (switched capacitor) Sigma-Delta modulator with a
1-bit quantizer and oversampling ratio of 64 to 2048. The first integrator features Correlated Dou-
ble Sampling to defeat flicker noise and perform auto-zeroing function. The modulator is followed
by a decimation filter which reduces the sampling frequency by a factor of the oversampling ratio,
to the nominal output sampling frequency. The Decimator consists of a 4th order SINC decima-
tion stage with a programmable factor of up to 128 followed by four cascaded stages of Half-Band
filters realizing a factor of 16. Sampling rates up to 96kHz are possible thanks to the selectable
oversampling ratio. The theoretical discrete-time model exhibits a Signal-to-Quantization ratio of
141 dB, with the target SNR to be at least 113dB over the entire temperature range. The converter
has been implemented in a radiation tolerant 0.15μm CMOS process of Atmel using a well estab-
lished and rigorous mixed-signal design flow. The analog part has been hardened using dedicated
process options, specific devices and special design rules. The digital part has been hardened using
hardened standard cell libraries and triple-mode redundancy in all blocks.
Primary authors: Mr HACHEMI, Adel (ASTUS S.A.); Dr DADALIARIS, Antonis (ISD S.A.); Dr
FRAGOPOULOS, Dimosthenis (ISD S.A.); Mr MAKRIS, Konstantinos (ISD S.A.); Mr CRESPY, Laurent
(ASTUS S.A.); Mr KARAOLIS, Makis (ISD S.A.); Ms DOKIANAKI, Olga (ISD S.A.)
Co-authors: Dr GLASS, Boris (ESA-ESTEC); Dr PAPADAS, Constantin (ISD S.A., ASTUS S.A.)
Presenter: Mr MAKRIS, Konstantinos (ISD S.A.)
Session Classification: Data Converters
Track Classification: AMICSA 2014
July 5, 2022 Page 7AMICSA 2014 - F … / Report of Contributions Scalable Sensor Data Processor: A …
Contribution ID: 7 Type: Poster
Scalable Sensor Data Processor: A New Mixed-Signal
Processor ASIC for Harsh Environments
Monday, 30 June 2014 14:40 (40 minutes)
In recent years, ESA has pursued the development of technologies for next-generation space Dig-
ital Signal Processing (DSP). One of those developments, the Massively Parallel Processor Bread-
board (MPPB), demonstrated European DSP cores as well as scalable Network-On-Chip (NoC)
technology for large Systems on Chip (SoC) and included space typical features such as SpaceWire
interfaces, ADC/DAC bridges and more. In a subsequent activity aimed at development of library
elements for IMEC’s DARE180 technology, a DSP prototype chip was developed in order to prove
the key elements of MPPB in DARE180 based silicon, and pave the way towards future space DSPs
based on the demonstrated technologies.
The Scalable Sensor Data Processor (SSDP) is the first of a new generation of such processors,
featuring an architecture very similar to MPPB (LEON General Purpose Processor (GPP), 2 VLIW
Xentium(R) DSP cores, high-bandwidth NoC, space typical interfaces (SpaceWire, ADC/DAC, CAN,
SPI and others) for the digital part. Like the prototype, the ASIC will be based on DARE180 tech-
nology which allows incorporation of analogue / mixed signal elements. It is expected that several
mixed signal blocks will be integrated, such as a fast (100 MHz) ADC for instrument data acqui-
sition, a second slow (ca 100 kHz) ADC with multiplexers for housekeeping data acquisition, and
additional circuitry for connection to external sensors. The ASIC will run at a target clock speed
of up to 100 MHz, providing in excess of 1 Giga-Ops for 16-bit data and 500 MOps for 32 bit fixed
point data. The GPP will provide a floating point unit, and on-chip memories will be provided for
fast data access in addition to external memories such as SDRAM, SRAM, and PROM. The ASIC
will feature high radiation hardness and reliability as well as low power consumption. The devel-
opment, which started in Q1/Q2 2014, is expected to provide prototype chips towards the end of
2015, followed by flight models about 1 year later.
Primary author: TRAUTNER, Roland (E)
Co-authors: GLASS, Boris (European Space Agency); Dr JANSEN, Richard (ESA/ESTEC)
Presenter: TRAUTNER, Roland (E)
Session Classification: Poster Session
Track Classification: AMICSA 2014
July 5, 2022 Page 8AMICSA 2014 - F … / Report of Contributions 180nm CMOS Mixed-Signal Radiat …
Contribution ID: 10 Type: Oral
180nm CMOS Mixed-Signal Radiation Hard Library
as base for a full ASIC supply chain
Monday, 30 June 2014 16:00 (20 minutes)
In recent years the importance of mixed-signal ASIC supply for Space Applications in Europe has
grown. Since there is a trend that Europe should be more independent from other worldwide
sources in obtaining these components on the market. IMST is actually working together with
TESAT Spacecom towards a mixed-signal library as part of an ESCC qualified ASIC supply chain.
This paper presents the IP blocks of IMST which are developed using innovative design and ra-
diation hardened techniques. These blocks are going to go through a program of evaluation and
qualification tests. The radiation hardened library of IMST, called HARD Library (HARD= Hard
Against Radiation Design is built from I/O cells for 3.3V and 5.0V supply voltages, reconfigurable
multifunctional operational amplifier, voltage and current references, memory cells, data convert-
ers and other analog and digital IP blocks, which will be described in this paper. The HARD Library
is based on the 180nm CMOS technology from XFAB, which is a modular mixed signal high volt-
age technology. It supports operation by negative supplies, which is one of the characteristics of
the HARD Library elements. Another feature of this technology is offering different modules for
low power, high temperature, high voltage and non volatile memory all in one platform. XFAB’s
180nm CMOS technology is already tested with good results against radiation effects. In this paper
first radiation test results of the IP blocks will be presented as well as scenarios about the design
flow of the HARD Library. Since the project is still in progress, evaluation test results are not
available yet. Finally the paper will show IMST´s capability to operate as a supplier for full space
qualified ASIC‘s to the market, handling the full supply chain in one hand.
Primary author: STEINKAMP, Jan (IMST)
Co-authors: Ms OIKONOMOPOULOU, Eleni (IMST GmbH); Mr HENKEL, Frank (IMST GmbH); Mr
LÜCK, Volker (TESAT Spacecom)
Presenter: STEINKAMP, Jan (IMST)
Session Classification: Radiation Hardened Technology for Mixed-Signal IC
Track Classification: AMICSA 2014
July 5, 2022 Page 9AMICSA 2014 - F … / Report of Contributions A radiation-tolerant Point-of-Load …
Contribution ID: 11 Type: Oral
A radiation-tolerant Point-of-Load buck DCDC
converter ASIC
Tuesday, 1 July 2014 14:20 (20 minutes)
The High Energy Physics Experiments at the Large Hadron Collider (LHC), the most powerful par-
ticle accelerator installed at CERN in Geneva, Switzerland, are in an exciting data taking phase but
are also preparing upgrades to improve their performance. Their complex assemblies of detector
systems make extensive use of electronics components located in a severe radiation environment
and in a magnetic field of up to 40,000 Gauss. Power distribution is a real challenge: other than
radiation and magnetic field tolerant, the distribution network components have to be small and
light (low mass and footprint) and have EMC performance sufficient not to affect the low noise
of the sensitive read-out electronics. For this application, CERN has developed a custom Point-of-
Load (POL) DCDC converter satisfying all the above requirements.
The POL converter is a single-phase buck topology built around an ASIC designed by CERN in
a commercial CMOS technology with high voltage capabilities. This circuit, named FEAST2, em-
beds on the same 2.8 x 2.88 mm2 silicon both the power switches, bootstrap diode and the control
circuitry. Capable of operating from an input voltage of 5 to 12V, it has a selectable output voltage
range between 0.6 and 5V and can provide up to 4A of output current (within the limit of 10W out-
put power). The switching frequency can be selected in the range of 1-3MHz, the best compromise
between efficiency and EMC performance being reached at around 1.8MHz. The bandwidth of the
feedback loop, at 150kHz, is sufficiently large to ensure excellent transient regulation. The high
switching frequency makes it compatible with the use of small air-core inductors of 200-400nH,
which are required to enable its use in the 40,000 Gauss magnetic field of the LHC experiments.
In terms of protection features, the circuit integrates a cycle-by-cycle Over-Current Protection
(OCP) and an Over-Temperature Protection (OTP), as well as Under-Voltage Lock-Out (UVLO)
preventing the converter to turn on in the absence of a sufficient input voltage. Communication
with the system embedding the DCDC is ensured by an Enable input (to turn it on/of) and a Pow-
erGood (PG) output flag, both signals being compatible with CMOS logic levels up to 3.3V. The PG
is asserted when the output voltage is in the range of +-6.5% around the nominal.
Radiation tolerance is achieved with a careful choice of the used CMOS technology (5 candidate
processes were probed for different radiation effects) and with the systematic use of hardness-by-
design techniques. Enclosed Layout Transistors (ELTs) have been employed to limit Total Ionising
Dose (TID) effects in all the control electronics, while adequate sizing, triplication and other ap-
propriate redundancy mitigate the impact of Single Event Effects (SEE). As a result, the circuit has
been qualified for TID levels in excess of 200Mrad(SiO2) and for displacement damage up to 5-8e14
n/cm2 (1MeV-equivalent neutrons). SEE qualification has been performed at the high penetration
heavy ion beam of CRC, Louvain-la-Neuve, up to an effective LET of 65 MeVcm2mg-1. No destruc-
tive events have been ever observed on any of the successive generations of prototypes exposed,
evidencing how the devices available in the technology are free from Single Event Burnout (SEB)
or Gate Rupture (SEGR). Actually the high voltage transistors have been also directly tested for
SEB sensitivity at the beginning of the development. The last and production-ready revision of
the circuit, FEAST2, is also free from any Functional Interrupt (SEFI): the converter continuously
provided on-specs output voltage while exposed to a cumulative fluence of 126e6 ions/cm2 in the
LET range between 10.2 and 65 MeVcm2mg-1. During the irradiation, occasional transients were
observed at the output of the converter, of an average duration below 2us and of amplitude below
+10%/-20% of the nominal output voltage. This result was possible after having deeply studied the
July 5, 2022 Page 10AMICSA 2014 - F … / Report of Contributions A radiation-tolerant Point-of-Load … sensitivity of previous prototypes, in particular using pulsed laser to map the sensitive nodes. The FEAST2 ASIC is now fully qualified as production-ready, and its production and distribution to the HEP experiments in the form of a full plug-in DCDC module is starting in the second quarter of 2014. Primary authors: FACCIO, Federico (CERN); BLANCHOT, Georges (CERN); MICHELIS, Stefano (CERN) Co-author: TROYANO PUJADAS, Isaac (CERN) Presenter: FACCIO, Federico (CERN) Session Classification: Applications for Radiation Hardened Analogue and Mixed-Signal ASICs Track Classification: AMICSA 2014 July 5, 2022 Page 11
AMICSA 2014 - F … / Report of Contributions The development of a radiation tol …
Contribution ID: 12 Type: Oral
The development of a radiation tolerant low power
SRAM compiler in 65nm technology.
Monday, 30 June 2014 16:40 (20 minutes)
With the upcoming upgrades of the LHC experiments, it will be necessary to improve the perfor-
mance and reduce the power consumption of the detector readout electronics. CERN has chosen
to use a 65nm technology for part the new generation ASICs targeted to these upgrades. For
this technology the SRAM memories within the readout circuitries need special attention as the
commercially available IP blocks don’t give the necessary radiation tolerance.
This paper will describe the design of a technology independent SRAM compiler design plat-
form with a custom SRAM design underneath. The generated SRAMs have clock synchronous
write/read operations and pseudo dual-port addressing. They are implemented in the LP (Low
Power) version of the technology and are designed to be radiation tolerant to reduce excessive
power leakage due to TID (Total Ionizing Dose) and to minimize the impact of SEE (Single Event
Effects) in the memory address decoding circuitry. An additional challenge for these SRAMs is to
keep the power consumption to a minimum whilst maintaining the radiation tolerance.
Primary author: Mr BROUNS, Robin (imec)
Co-authors: MARCHIORO, Alessandro (CERN); Mr THYS, Geert (imec); KLOUKINAS, Kostas
(CERN); BONACINI, Sandro (CERN); Mr VERHAEGEN, Staf (imec); Mr REDANT, Steven (imec)
Presenter: Mr BROUNS, Robin (imec)
Session Classification: Radiation Hardened Technology for Mixed-Signal IC
Track Classification: AMICSA 2014
July 5, 2022 Page 12AMICSA 2014 - F … / Report of Contributions Development of an High Speed an …
Contribution ID: 13 Type: Poster
Development of an High Speed and High Resolution
ADC for Image Processing Applications
Monday, 30 June 2014 14:40 (40 minutes)
Today there is no space suitable solution in Europe for high speed (e.g. 20Msps) and high resolution
(16 bit) Analogue-to-Digital Converters (ADC) to process and digitise analogue output signals from
image sensors or other high resolution instruments. Such devices would enable new applications
with higher performance. In addition it would guarantee European independence and it would
reduce the dependence on COTS devices and their associated screening costs and time.
Therefore ESA has initiated a program for developing such an high-speed and high resolution ADC.
In the framework of this program SPACE ASICS (Greek) will develop such an ADC together with
Kayser-Threde GmbH (Germany) and others.
The paper will present the project objectives, planning and will define and present the key perfor-
mance requirements for the ADC under development. Because the ADC application is targeted to
image processing with CMOS and CCD sensors an analogue front end is also implemented in the
ADC providing typical analogue processing as used for readout of imaging sensors. The paper will
present and discuss this analogue front end, including clamping, correlated double sampling and
adjustable offset and gain correction. Furthermore all other functional requirements are presented
and discussed.
Verifying the characteristics of an ADC with such high dynamic performance can prove very chal-
lenging as the evaluation environment has to be designed such that it provides even better perfor-
mance than the device-under-test (DUT). Eliminating any kind of noise caused by signal generators
or external circuitry is a key aspect designing the test environment. Additionally, the choice of
suitable measurement techniques and test conditions is important for an accurate determination
of the performance characteristics and demanded test equipment. The abstract will present veri-
fication methods and algorithms and will show previous test results, performed for evaluation of
the test environment. Conclusions for testing of the ADC are drawn from the results and evalua-
tion of the acquired data. For each sub-part of the evaluation board including the corresponding
signal generators that generates the input signal, solutions are presented how the necessary per-
formance and functionality can be achieved. Furthermore, selected measurement techniques will
be presented that have proven to be suitable to verify and characterize the 16-bit analog-to-digital
converter and provide a good basis for the development of the final evaluation environment once
the prototypes of the ADC are realized.
Furthermore the paper shall address potential users of the ADC and shall present the procedure of
a market survey to be performed in the framework of the project. Potential users shall be identified
and appropriate feedback about performance and functionality of the ADC shall be requested.
Primary authors: Mr KOELNBERGER, Andreas (Kayser-Threde GmbH); Mr HEYER, Heinz-Volker
(Kayser-Threde GmbH); Mr TELLE, Holger (Kayser-Threde GmbH)
Co-authors: Mr GLASS, Boris (ESA); Mr SARRIS, Emmanuel (SPACE ASICS); Mr KOTTARAS,
George (SPACE ASICS)
Presenter: Mr HEYER, Heinz-Volker (Kayser-Threde GmbH)
Session Classification: Poster Session
July 5, 2022 Page 13AMICSA 2014 - F … / Report of Contributions Development of an High Speed an … Track Classification: AMICSA 2014 July 5, 2022 Page 14
AMICSA 2014 - F … / Report of Contributions FAIR, a front-end ASIC for infrared …
Contribution ID: 15 Type: Oral
FAIR, a front-end ASIC for infrared detector readout
Tuesday, 1 July 2014 09:30 (20 minutes)
In the FAIR project (Front-end ASIC for Infrared detector Readout), an IC is developed for the read-
out of state-of-the-art NIR/SWIR detectors for future Earth observation missions and astrophysics.
The chip consists of a high-resolution ADC with integrated offset correction and adjustable gain,
and voltage regulators to generate bias/reference voltages for the detector. The chip is designed to
operate in an extremely large operating range from -218 degrees Celcius up to 50 degrees Celsius.
The original mission goal was for the Exoplanet Characterization Observatory (EChO). In order to
fulfil the challenging stability and low-noise requirements, the read-out electronics needed to be
placed as close to the detector as possible, thus reducing electromagnetic interference (EMI) and
gaining overall signal integrity. The close proximity to the cooled detector requires the read-out
electronics to operate at an equally reduced temperature. Considering that the target atmospheric
gases addressed by EChO - CH4, CO, CO2 and H2O - are the same as addressed by current and
future in Earth-observation missions in the SWIR-IR spectral range (e.g. ESA Sentinel-5, ESA Car-
bonSat, CNES MicroCarb), it is clear that the FAIR chip also offers interesting opportunities for
application in future Earth observation missions. The FAIR chip can be placed naturally into the
existing electronic readout environment for application to other future IR detectors, replacing and
significantly miniaturizing the analog electronics, fitting in the on-going trend of integration in
detector electronics for space instrumentation in general: obvious advantages are the reduction of
power consumption, volume and weight. The ADC has a 16-bit resolution and offers a sampling
rate of 1 Megasample per second. It is designed for an ultra-low power consumption of 16mW.
The ADC analog circuitry area is 2 square mm. Special analog layout techniques were used to en-
sure radiation hardness, and all digital circuitry was place&routed using the rad-hard IMEC DARE
library.
Primary author: Dr SCHRADER, Jan-Rutger (SRON Netherlands Institute for Space Research)
Co-authors: Dr SCHINKEL, Daniel (Axiom IC Teledyne Dalsa); Mr GARAKOUI, Seyed Kasra (Axiom
IC Teledyne Dalsa)
Presenter: Dr SCHRADER, Jan-Rutger (SRON Netherlands Institute for Space Research)
Session Classification: Applications for Radiation Hardened Analogue and Mixed-Signal
ASICs
Track Classification: AMICSA 2014
July 5, 2022 Page 15AMICSA 2014 - F … / Report of Contributions Analog Front End Integrated Circu …
Contribution ID: 16 Type: Poster
Analog Front End Integrated Circuits for Mixed
Signal Spacecraft Applications
Monday, 30 June 2014 14:40 (40 minutes)
Mixed signal spacecraft systems typically involve a digital processing portion to execute algorithms
based on external events and the Analog Front End (AFE) that provides the interface between the
benign digital processor environment and the “real world”. The digital processor is typically op-
timized for high speed computations using a low voltage process that helps reduce the power
consumption. The analog interfaces in some applications are higher voltages to minimize sus-
ceptibility to interference. The digital processing can be a sequential instruction microprocessor
which realizes algorithms in software or an FPGA fabric that can simultaneously process several
data streams. An analog front end (AFE) might consist of operational amplifiers, current sources,
data converters, power drivers. Typical applications include telemetry for applications including
attitude control, motor control and position sensing, and power control. The sensor interface is
rarely compatible directly to the processor I/O so some level of buffering is necessary. Buffering
is also required to support redundancy which may involve cold sparing.
There are various degrees of specialization that can be supported by an AFE; the most flexible
being a design made up of single function parts that are uniquely configured for each application.
The highest level of integration is a custom IC designed for a specific application; this solution
affords the least degree of flexibility if the requirements change. An AFE approach that offers
a high degree of integration and a high degree of flexibility would be an integrated circuit with
commonly used analog interfaces that are configurable. An efficient partitioning of the analog
and digital functions minimizes the hard coded logic within the AFE and moves as much of the
configurability to a Hardware Description Language (HDL) defined digital part such as an FPGA.
HDL based logic tends to be more intuitive than schematic based logic using LSI parts for example.
A spacecraft FPGA is designed to be radiation tolerant with redundant logic paths; it uses a small
geometry process to improve circuit density. The FPGA gate count can be sized to an application
or a group of applications to reduce cost and increase gate utilization. When the AFE is offered
as a standard prequalified part as opposed to a custom part, it has the advantage that it does not
require development so non-recurring engineering is reduced and time to market and schedule
risk are also reduced. While the standard part AFE may not be fully utilized in every application,
the level of integration for using even a portion of the circuits is usually a reduction in size over
the use of single function parts.
There are many spacecraft functions that can benefit from an AFE. Sensor arrays such as health
monitoring are suitable for sequential sampling as opposed to continuous monitoring. A flexible
sensor interface AFE includes an analog multiplexer, a conditioning amplifier and an analog to
digital converter. Passive sensors require an exciter such as a current source and should support a
“four wire” measurement for high accuracy. Maximum flexibility can be designed in by allowing
each AFE I/O to serve as a current source, a differential input or a single ended input. A position
sensor such as a resolver or a coil current sensor in a motor likely requires continuous sampling
if the position and or current is used in a servo control system that also drives the motor coils.
A sigma delta converter with oversampling works well in these applications since the sampling
modulator can be implemented in the AFE and the filter can be implemented in the FPGA. The
FPGA can control the degree of the decimation to obtain a flexible compromise between resolution
and sample rate. The FPGA can also process multiple ADC paths simultaneously and not burden
the control loop state machine with the ADC sinc3 filter processing. For power control, the non-
volatile programming of an FPGA can be exploited to bring up power rails in sequence and to
mitigate faults if the occur. The AFE can provide voltage and current supervision and DACs for
power supply margining. The AFE can also provide linear control for slewing the output of solid
state circuit breakers to reduce power bus transients and open circuits in the event of a fault.
July 5, 2022 Page 16AMICSA 2014 - F … / Report of Contributions Analog Front End Integrated Circu … The use of a standard integrated circuit AFE paired with a configurable FPGA takes advantage of a high level of integration when the partitioning of the analog and digital functions provides IC process optimization for the implementation of the digital and the analog functions. Higher integration reduces parts count which improves reliability and reduces size and weight of the spacecraft electronic modules. This presentation discusses the topics above and provides examples to demonstrate the concepts. Primary author: Mr FERGUSON, Bruce (Electrical Engineer at Microsemi Corp) Presenter: Mr FERGUSON, Bruce (Electrical Engineer at Microsemi Corp) Session Classification: Poster Session Track Classification: AMICSA 2014 July 5, 2022 Page 17
AMICSA 2014 - F … / Report of Contributions Use of IHP’s 0.25 µm BiCMOS Pro …
Contribution ID: 17 Type: Oral
Use of IHP’s 0.25 µm BiCMOS Process in the
Development of European LVDS Devices
Tuesday, 1 July 2014 11:50 (20 minutes)
Transmission of large amount of data is extensively used in communication among spacecraft and
satellite onboard systems during a mission. LVDS (Low-Voltage Differential Signaling) Drivers
and Receivers are key to provide means of sending/receiving data along twisted pair cable at very
high data-rates with low power and excellent EMI performance. Rad-tolerant and Rad-hard ANSI
EIA/TIA 644A complaint LVDS Drivers and Receivers products are essential in an extensive range
of space applications. Typical applications with such needs are SpaceWire and clock distribution
networks.
The purpose of this activity is the development of an LVDS Octal repeater in the frame of ESA’s
and ECI’s European LVDS Driver Development intended to be used in space applications and built
in IHP’s 0.25-um BiCMOS process technology which has a good performance in terms of radiation,
for both total dose and single event effects. Previous tests on this technology show no degradation
up to 300Krad of total ionization dose (TID) and a single event latch-up (SEL) immunity up to
84MeV cm2 mg-1 at least.
The key features of the octal LVDS repeater include cold sparing (essential for redundant systems
architecture), up to 250MHz signaling rate per channel allowing for 500Mbps transfer rates over
SpiceWire, 3.3V single power supply, fast propagation delay, low channel to channel skew, TRI-
state output control, extended common mode on LVDS receivers and the minimum ESD tolerant
rating of 8kV for human body model (HBM), 250V for machine model and +/- 500V for field induced
charge device model.
In order to validate and characterize the technology for the extended ESD tolerance an additional
test vehicle chip has been built in the frame of the activity, with a set of ESD test vehicles that
include NMOS clamps, PMOS clams, and diodes.
Primary author: Mr LÓPEZ, Jesús (Arquimea)
Co-authors: Mr GONZÁLEZ, Daniel (Arquimea); Mr LÓPEZ, Demetrio (Alter); Mr CORDERO,
Enrique (Alter); Mr KORNDÖRFER, Falk (IHP); Mr ILSTAD, Jorgen (ESA); Mr CIRILLO, Maurizio
(IHP)
Presenter: Mr LÓPEZ, Jesús (Arquimea)
Session Classification: Applications for Radiation Hardened Analogue and Mixed-Signal
ASICs
Track Classification: AMICSA 2014
July 5, 2022 Page 18AMICSA 2014 - F … / Report of Contributions High performance analog Front En …
Contribution ID: 18 Type: Oral
High performance analog Front End ASIC for
interfacing with a Si Drift Detector and the control
electronics
Monday, 30 June 2014 10:50 (20 minutes)
In the frame of the LOFT (Large Observatory For x-ray Timing) program, IRAP, CNES and Dol-
phin Integration have collaborated to develop a high performance ASIC (SIRIUS2) for interfacing
Silicon Drift Detectors (SDDs) with the digital back-end
LOFT was candidate X-ray mission for the M3 slot of the Cosmic Vision program of the European
Space Agency. It will be proposed again for the M4 mission. LOFT is designed to study the neu-
tron star structure and equation of state of ultra-dense matter and to explore the conditions of
strong-field gravity.
The primary enabling technology for the Large Area Detector (LAD) is the SDDs developed for
the Inner Tracking System in the ALICE experiment of the Large Hadron Collider at CERN, by
scientific institute INFN Trieste, Italy.
The project targets a 10 m² detector array for 2 to 80 keV Xrays detection at high sensitivity (50
– 200 eV) and good energy resolution (limited by electronic noise, itself limited by EOL detector
leakage current) with a dead time « 1% at 1 Crab.
Such a system will require 500 k to 600 k SDD detectors managed by 35 k to 40 k ASICs.
The collaboration among IRAP, CNES and Dolphin Integration targeted these ASICs interfacing
the SDDs and the digital back end on the satellite.
SIRIUS2 embeds 16 Analog Front Ends (AFEs,) a 12-bit ADC for digitization, DACs for the genera-
tion of the threshold for the minimum detectable event, low noise comparators, multipliers and the
full digital interface used to control the AFEs and to read the measures. The ASIC was developed
using the 180nm mixed technology of TSMC.
The harder performances of SIRIUS2 are the energy resolution of 200eV @ 6keV (requiring a very
high performance in term of noise corresponding to an ENC of 17 electrons end of life of the SDD),
the very low power consumption (lower than 650 µW/channel) and a full scale higher than 22200
electrons.
In term of analog design, since the SDD deliver current pulses of low intensity and short duration,
the AFE uses an integrator to accumulate the corresponding charge in a capacitor to deliver a volt-
age output. This structure is called a charge preamplifier, and will be noted CPA here below.
In order to add gain and improve signal to noise ratio, the CPA is usually followed by a pulse
shaper, working as a matched filter.
The output of the CPA plus the shaper is a voltage pulse. Depending on the application, this pulse
is either compared to a threshold and sent to an event counter, or sampled and digitized. In order
to capture the energy of the Xray events, it is required to detect the pulse maximum and hold the
voltage by a Peak and Hold, or P&H here below.
Critical performances have been analyzed and quantified.
Noise contributions have been estimated and rated.
It has been highlighted that important characteristics such as noise, gain, speed, power, area have
conflicting requirements and that some trade-offs must be carefully balanced.
The resulting formulas will be presented, in parallel to simulations, in order to highlight the tech-
nical solutions that have been chosen for LOFT project requirements.
The CPA has been designed using switched reset structure based on a gain capacitor of 75 fF. This
offers a good balance between preamplifier gain and dead time requirements, while keeping tran-
sient behavior of pulse shaper within acceptable limits. Instead of generating a tiny continuous
leakage, the capacitor is regularly shorted for a small time (after detection, when leakage current
has generated an excessive offset at CPA output). This solution is the best in term of noise with a
drawback link to the dead time due to the reset. The noise performance of around 20 ENC at tau
of 2 µs, for a dead time lower than 0.7 % meets the initial specifications.
July 5, 2022 Page 19AMICSA 2014 - F … / Report of Contributions High performance analog Front En … For the SHAPER the best trade off comes with CR-RC² topology. Higher the orders lower the ENC. But global optimization requires significant gain in the shaper. Higher order filters (CR²-RC2 or CR-RC3) have lower peak gain. Hence it is necessary to boost resistors ratios, severely loading the CPA or generating higher shaper noise. Simulations have confirmed that total signal to noise ratio was not improved by higher order shapers. For the P&H, a derivation-based peak detector followed by a switched capacitor hold cell will feed the analog to digital converter. The measurement with the SDD have been done at room temperature (≈25°) showing a best value obtained in term of noise of 24.5 e- rms with shaping time 4 us. The gain linearity is very good and the gain is stable over temperature range. The power consumption achieved is lower than 580 µW per channel at room temperature. Primary author: BONZO, Andrea (Dolphin Integration) Co-authors: Mr CROS, Alain (IRAP); Mr GAILLARD, Christophe (Dolphin Integration); Mr RAM- BAUD, Damien (IRAP); Mr BARRET, Didier (IRAP); Mr GRAND, Emmanuel (Dolphin Integration); Mr MOUTAYE, Emmanuel (IRAP); Mr SEYLER, Jean-Yves (CNES); Mr LETUVEE, Nicolas (Dolphin Integra- tion); Mr BODIN, Pierre (CNES); Mr CLEDASSOU, Rodolphe (CNES); Mr MORANDINI, Yvan (Dolphin Integration) Presenter: BONZO, Andrea (Dolphin Integration) Session Classification: Applications for Radiation Hardened Analogue and Mixed-Signal ASICs Track Classification: AMICSA 2014 July 5, 2022 Page 20
AMICSA 2014 - F … / Report of Contributions A mix-signal radhard micro- …
Contribution ID: 19 Type: Oral
A mix-signal radhard micro-controller: DPC
Tuesday, 1 July 2014 14:40 (20 minutes)
Thales Alenia Space is engaged in the development of a radiation hardened mixed-mode circuit:
the DPC (digital programmable controller). This device is a major breakthrough in the availability
of radiation hardened highly integrated micro-controller.
The construction of the DPC is the result of 4 party project involving Imec, ICsense & Thales Alenia
Space under an ESA development. This component uses the Imec RHBD DARE on UMC 0.18µ
library and analog IP designed full custom by ICsense. The effective performance characterization
of the DPC is currently evaluated in Thales Alenia Space laboratory.
The DPC is an essential building block for the development of intelligent RTU and other (power)
distribution units in LEO & GEO satellites. Its large set of communication interface makes it us-
able in a broad range of applications such as scientific payload control, motors, actuators, battery
management, power management … wherever a decentralized control makes the overall solution
more efficient.
The presentation covers the key features of the DPC that have been made possible thanks to some
extensions of the DARE library such as DPRAM, IO and clock gating. The analog functions such
as ADC, DAC, PLL & band gap have been designed such as to minimize the amount of external
components needed around DPC (target being a system on chip). The E2prom containing the hard-
ware configuration bitstream and the firmware remains, for this 1st generation, still an external
device. Extreme care was taken to SET hardening of the critical analog functions: ICsense having
developed automated & systematic charge injection verifications.
First tests results will be presented together with the roadmap to complete the evaluation for space
use and the path to deliver flight models.
Project organisation
Imec not only has provided the RHBD DARE on UMC 0.18µ library, but also extended it with ad-
ditional features. Dual port memories are being used to transparently perform memory scrubbing
in a seamless manner for the processing unit. The DPC embeds 95Kbytes of memory split over
several banks. Clock gating cells have been also added. As the DPC embeds a large range of fea-
tures, power consumption may become an issue if all of them would be active simultaneously. At
boot time, a hardware configuration is loaded in the circuit to only deliver clock toward functions
relevant to the target application.
Imec also performed top level layout integrating digital netlist & analog macros, performing DRC
to check for compliance to particular radiation hardening rules and finally the interface with UMC
foundry.
ICsense has designed a large set of analog IP blocks which are included on chip. Concerning IO
offered to the user, there are 4 analog to digital converters 13bits-1MSps with input multiplexing
functions. There are also 3 current steering DAC each 12bits-50kSps / 8 bits-1MSps. As supporting
function the DPC also includes an on-chip 100kHz RC oscillator for applications that do not require
high precision frequency reference. This frequency reference is internally multiplied with a PLL
delivering the internal master clock of the circuit. All these function are obviously supported by
an on-chip bandgap. A set of internal low-drop voltage regulators converts the incoming 3.3V into
+1.8Vdc to supply the digital core and to deliver “noise-less” supply to critical analog functions.
This extensive set of analog function makes DPC a rather standalone system-on-chip (exception
being for now the external E2prom).
July 5, 2022 Page 21AMICSA 2014 - F … / Report of Contributions A mix-signal radhard micro- … Besides classical RHBD rules such a guard rings (Latchup) & margins for Vt shifts (dose up to 100krad), ICsense has developed an powerful set of extension on top of (Cadence/Mentor) simula- tion tools to perform systematic charge injection verifications on each nodes of the circuit. ICsense has completed the design, layout & verifications. The 2 analog macros were delivered to Imec for integration into the final chip layout. Thales Alenia Space Belgium has developed the RTL code to glue up all IP: the 16bits OpenMSP430 processor, mil-1553b, UART, CAN interfaces, memories, multipliers… On top of the classical simu- lation at RTL, the DPC has been extensively validated on 2 FPGA platforms. The first one was used to validate all interaction modes foreseen in the DPC feature list. The second one was to integrate the DPC with its software development environment. Challenge for such a complex mix-mode design resides into the verification of interfaces between analog macros and digital functions. This problem was tackled by the exchange of Wreal models simulating the behavior of analog functions to be used in digital simulations. In the other way, stubs of RTL code have been delivered to simulate analog functions with their interface to digital functions. Foundry was done by UMC & packaging has taken place at HCM. Wafer probe & package testing used facilities of µTest. The component is now back into the labs & alive: tests ongoing. Primary authors: Mr VAN ESBEEN, Alain (ThalesAleniaSpace); Mr FOSSION, Marc (ThalesAleni- aSpace) Co-authors: Mr MONTELEONE, Claudio (ESA); Mr GEUKENS, Eldert (ICsense); Mr JANSEN, Richard (ESA); Mr REDANT, Steven (IMEC); Mr GEERTS, Yves (ICsense) Presenter: Mr FOSSION, Marc (ThalesAleniaSpace) Session Classification: Applications for Radiation Hardened Analogue and Mixed-Signal ASICs Track Classification: AMICSA 2014 July 5, 2022 Page 22
AMICSA 2014 - F … / Report of Contributions Assessment of Mixed Signal Techn …
Contribution ID: 20 Type: Oral
Assessment of Mixed Signal Technology
Monday, 30 June 2014 10:10 (20 minutes)
In 2013, within the ECI (European Component Initiative) program of the European Space Agency,
the activity “Assessment and characterization of Mixed Signal Technology” has been initiated. In
this paper the activities performed for the assessment and selection of an European mixed signal
technology suitable for the development of ASICs for space applications will be described. In order
to drive the assessment and selection process three different surveys have been carried out. The
main results will be presented in this paper.
In the first survey a comparative assessment, the availability of several existing European mixed
signal technologies has been performed. The assessment focused on the availability (access, licens-
ing, condition for use, process lifetime, process options, supported tool chain, etc.), environment
supported (voltage and temperature range, radiation tolerance, ESD and EMC levels, etc.), quality
features (wafer thickness, yield, FIT, PID, failure analysis support, process stability, etc. ), analogue
(Spice model accuracy, devices primitives availability, simulators model supported, etc.) and digi-
tal (gate density, power consumption, clock frequency, supply voltage range, leakage current, cell
libraries, model accuracy, supported tool chain, sign-off, etc.) performances.
In the second survey, inputs covering the needs for mixed-signal ASICs from the space community
and the Agency’s planned missions has been collected.
In last survey, information about the existing rad hard libraries and design kits in terms of primitive
devices, SEEs, TID and reliability performances have been collected. Six European foundries have
been contacted: Atmel, Austria Micro Systems (AMS), IHP Microelectronics, ON Semiconductor,
Telefunken Semiconductor and XFAB; the data obtained from a total of 18 technology processes
have been collected and analysed.
Based on the review of the data obtained by the collected questionnaires and by consideration
that multiple mixed signal ESA and national Space Agencies activities are currently on-going on
several technologies, the CMOS High Voltage 180nm process with NVM option by XFAB has been
chosen for further characterization in phase 2. The work will consist in the design of a test vehicle
containing primitive devices and simple circuits. The characterization will consist of I-V and C-V
curve extraction, end of life (EOL) test, Total Ionization Dose (TID) test, Single Event Transient
(SET) evaluation in term of pulse width and charge injected and it will be aimed to analyze the
reliability and radiation test results. The final objective is to extract electrical basic analogue device
models and to incorporate those into the design-kit.
Primary author: BIGONGIARI, Franco (SITAEL S.p.A.)
Co-authors: Mr BOATELLA POLO, Cesar (European Space Research and Technology Centre); Mr
BACCI, Maurizio (SITAEL S.p.A.); Mr INVERSI, Maurizio (SITAEL S.p.A.); Mr JANSEN, Richard (Eu-
ropean Space Research and Technology Centre); Mr DITTRICH, Rok (European Space Research and
Technology Centre)
Presenter: BIGONGIARI, Franco (SITAEL S.p.A.)
Session Classification: Need and Requirements for Radiation Hardened Analogue and Mixed-
Signal ICs
July 5, 2022 Page 23AMICSA 2014 - F … / Report of Contributions Assessment of Mixed Signal Techn … Track Classification: AMICSA 2014 July 5, 2022 Page 24
AMICSA 2014 - F … / Report of Contributions Radiation hardness tests of the …
Contribution ID: 21 Type: Oral
Radiation hardness tests of the CLARO-CMOS chip:
a fast and low power front-end ASIC for
single-photon counting in AMS 0.35 micron CMOS
technology
Monday, 30 June 2014 11:30 (20 minutes)
The CLARO-CMOS is a prototype ASIC primarily designed for single-photon counting with multi-
anode photomultipliers (Ma-PMTs). The chip features 5 ns peaking time, a recovery time to base-
line smaller than 25 ns, and a power consumption in the order of 1 mW per channel. It was devel-
oped in the framework of the LHCb RICH detectors upgrade at CERN, but also found application
in the readout of Silicon Photo-Multipliers (SiPMs) and microchannel plates.
The prototype, realized in AMS 0.35 micron CMOS technology, has four channels, each made of a
charge amplifier with settable gain (3 bits) and a comparator with settable threshold (5 bits) that
allow tuning the response of the chip to the gain spread of the Ma-PMT pixels. The threshold can
be set just above noise to allow an efficient single-photon counting with vacuum photomultipliers.
In the readout of SiPMs, the threshold can be set above the single photon signals, allowing to
count events with two or more photoelectrons with high efficiency and good separation of the
photoelectron peaks.
The CLARO-CMOS chip was fully characterized on the test bench. The chip was coupled to a
Hamamatsu R11265 Ma-PMT, the baseline photon detector for the LHCb RICH upgrade, and was
found able to read-out single-photon signals up to the maximum average rate expected in the LHCb
RICH (~10 MHz) with a low power consumption (~1 mW) and a negligible crosstalk between pixels.
In the LHCb RICH environment, over ten years of operation at the nominal luminosity expected
after the upgrade in Long Shutdown 2, the ASIC must withstand a total fluence of about 6x10^12
1 MeV n_eq/cm^2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation
effects on the CLARO-CMOS performance is therefore crucial to ensure long-term stability of the
electronics front-end.
We present results of multi-step irradiation tests with neutrons up to the fluence of 10^14 1 MeV
n_eq/cm^2, with protons up to the dose of 8 Mrad and with X-rays up to the dose of 8 Mrad.
During irradiation, cumulative effects on the performance of the analog parts of the chip and single
event effects (SEE) were evaluated. The chips were biased continuously and the chip threshold
voltages were measured regularly, in order to detect possible single event upsets (SEUs) affecting
the threshold DAC settings. Power consumption was also monitored online, and an additional
circuit provided protection against Single Event Latchup (SEL). S-curves were measured before
and after each irradiation step, to follow the evolution of counting efficiency, threshold shifts and
noise during the irradiation.
Primary authors: COTTA RAMUSINO, Angelo (Universita di Ferrara (IT)); GOTTI, Claudio
(Universita & INFN, Milano-Bicocca (IT)); PESSINA, Gianluigi (Universita & INFN, Milano-Bicocca
(IT)); FIORINI, Massimiliano (Universita di Ferrara (IT))
Co-authors: GIACHERO, Andrea (Universita & INFN, Milano-Bicocca (IT)); LUPPI, Eleonora (Uni-
versita di Ferrara (IT)); CASSINA, Lorenzo (Universita & INFN, Milano-Bicocca (IT)); TOMASSETTI,
Luca (University of Ferrara and INFN); MAINO, Matteo (Universita & INFN, Milano-Bicocca (IT)); Dr
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