Some New Analogic CNN Algorithms for PCB Quality Control
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Some New Analogic CNN Algorithms for PCB Quality
Control
TIMÓT HIDVÉGI and PÉTER SZOLGAY ‡
Analogic and Neural Computing Systems Laboratory, Computer and Automation
Institute, Hungarian Academy of Sciences, P.O.B 63, H-1502, Budapest, Hungary
E-mail: hidvegi@sztaki.hu
‡
Also with Image Processing and Neurocomputing Department Veszpém University,
Egyetem u. 10. Veszprém, Hungary
SUMMARY
In the production of a PCB different errors may occure. The detection of these
errors is time consuming and there is an increasing need to use a 100% quality
control in production. New analogic CNN algorithms were developed to detect the
short circuit and the misalignment errors. These analogic algorithms were tested
with software simulator, 20*22 CNN-UM chip and 64*64 CNN-UM chip by using
ALADDIN System.
1. INTRODUCTION
To meet the requirements of high production rate and the tight tolerances of PCB
(Printed Circuit Board) production Automatic Optical Inspection (AOI) systems are
generally used. The function of these systems is as follows: the faulty samples should be
selected and repaired or removed before each critical technological step of production.
The main AOI techniques [2], [5], [6], [7], [8], are as follows: (i) reference based
methods [4] (a comparison to a reference or to a good sample), (ii) non-referential
methods (rule based method) [3] and (iii) hybrid methods [7] are combination of the two
previous methods. Some hybrid methods based on CNN paradigm [10a], [10b] will be
shown in this contribution. In this application the high computing speed of the analog
VLSI implementation of the CNN microprocessors is used.
Some promising results were reported on, on layout error detection with CNN.
The detection of the minimal line width violations is a key problem. It was shown that a
lot of layout error detection rules could be reduced transformed to this problem [1]. The
basic idea of the break detection algorithm was that a wire has to be terminated in a pad,
in a via hole or in another wire [1]. The short circuit detection in a layout was based on
global properties. To solve this problem the whole interconnection of a circuit has to be
known. CNN is especially efficient in detecting local properties. An analogic algorithm isgiven to detect some types of short circuits [1]. The places of the ”H shape-type”
interconnections will be detected on the layout.
In this contribution two additional important PCB layout error detection
algorithms will be shown, namely a misalignment error detector [21] (to detect the
misalignment of artwork film to the drilled board) and a new and more general short
circuit detector [22] (where between two different nodes short circuits are detected by
using an analogic CNN algorithms.)
The analogic CNN algorithms were developed by using the ALADDIN
computation infrastructure to CNN-UM. The algorithm was written in high-level language
ALPHA [19], [20] and compiled and run by using the software simulator. If the algorithm
was run correctly in software environment, then the same algorithm code, with a bit tuned
templates could be downloaded [12] to the analog 64*64 [14], [15] (or earlier to 20*22
[13]) CNN-UM. We are going to show some running time data on real PCB examples.
The misalignment error detection algorithm is shown in section 2 and the short-
circuit detection algorithm in section 3, respectively. In section 4 two examples, some
measuring results and concluding remarks are given.
2. Misalignment error detection in printed circuit board fabrication by using an
Analogic CNN algorithm
The main steps of our misalignment error detection algorithm are considered. The
inputs of the analogic CNN algorithm are the artwork film and the drilled PCB.
Here we assume that the minimal size of a geometrical object is covered by 2-3
pixels (CNN cells). The flowchart of the layout error detection algorithm is shown in
Figure 1. Depending on the printed circuit board technology, different branches of the
analogic CNN algorithm are used.Load
the drilled PCB
+
artwork fitted PCB
See Figure 2 Fitting and average
n Is it a fill
type PCB?
Is the y
y diameter n
of PAD
white?
Logic AND Logic AND
between between
the two images the two images
Logic subtract invertion
between
Logic AND
the drilled and
between
artwork film
the two pictures
Logic AND
Logic OR between
between the result and
the two result drilled PCB
images
smkiller.tem
(1 iteration)
dilation.tem
(some iterations)
Displaying
the results
Figure 1 The flowchart of the misalignment detection algorithm of PCBsThe algorithm is built up of three parts, in which the first and last three steps are
common.
First, we download the images of drilled PCB, and the artwork film. The drilled
PCB image may be black&white or gray-scale. If the picture is a gray-scale image, we
have to convert it into a black&white one by using threshold-type operation like the
“averge.tem” template in [16]. The two images have to overlap each other in a very
accurate manner. Unfortunately, it is not accomplished in the course of scanning.
Therefore, we have to fit the two images. To provide proper alignment of the input images
they are shifted to the upper left corner of the checked area. The image is shifted until
some pixels touch the left as well as the top edge of the image. The “subroutine” of
shifting is given in Figure 2. [17]
Gray-scale to
black-white
image conversion
Place of examined
block object
Does the
black object reach n
the left edge
of the frame?
We move the
y object left by one pixel
Figure 2 Fitting the black object to the edge of the picture
The next algorithmic steps depend on the type of PCB.
If the artwork film is of “FILLED” type, then we use logic AND function between
the artwork film and the drilled PCB. In this case the pads have to have via-holes in the
image. Due to the AND function, the via-hole with black color and the edge of the pads of
the result is of black color. There are two possibilities. If the distance is large, then the
error found will be raunchy. We can see this phenomenon in Figure 3.PAD
AND
1.
ERRORS
AND
2.
Figure 3 AND function between the PAD and hole size of PAD
In Figure 3 two cases are represented. In the first example the distance between the
pad and the via-hole is bigger than in the second one. To avoid false error messages the
single black pixels are removed by the “smkiller.tem” template. These types of error do
not cause problem in course of assembling the components. Finally, to magnify the real
errors some dilatation steps were used to make the errors more visible.
If the artwork film is not of “FILLED” type and the pads do not have via-holes, then
we use logical AND function (Figure 4). Naturally, here we can use the “smkiller.tem”
template because of the insensibility of the smaller errors. We can remove the one-pixel
errors before the dilatation. After that the remainder pixels are real errors. We enlarge
these pixels with the “dilation.tem” template.
PAD
Drilled PCB
AND
NOT
AND
ERROR
VIA-HOLE
Figure 4. Search for error (the via-hole is black)If the artwork film is not of “FILLED” type and the pads do have via-hole, then we
use logical AND by the artwork film and the drilled PCB image (Figure 5). The output is
inverted in the next step. Then, we use the AND function between the result and the
drilled image again.
PAD
AND
ERROR
VIA-HOLE
Figure 5. Search for error (via-hole is white)
Unfortunately, this part of the algorithm does not detect the big difference between
the pad and via-hole if the hole size does not overlap the pad. Therefore, we subtract the
artwork film from the image of the drilled PCB (Figure 6)
Drilled PCB
Drilled PCB with
fitted artwork film
Result
Figure 6 Search for error (via-hole is white)
In the black&white image the value of black color is +1 and that of the white is -
1. So if we subtract a white color from the black one, then we get black objects.
Then, we unify the two types of error by using a logic OR.
Unfortunately, the errors can hardly be seen in a big picture. Therefore, we
increase these black areas with dilatation or by using the "recall" templates.3. Short circuit detection on printed circuit boards during the manufacturing
process by using an Analogic CNN Algorithm
The main steps of our short circuit detection analogic CNN algorithm can be seen
in Figure 7.
Load the
images
of top + bottom
Load the
reference image
Fitting and average
see in the text Logical AND
function between
reference image
and result image
Load the
image of marker
Are
there
y ERROR
Recall.tem on any pads on
top layer the PCB?
(~200 iterations)
n
Erosion.tem O.K.
(w*3 iterations)
Recall.tem on
bottom layer
(~200 iterations)
Erosion.tem
(w*3 iterations)
w: the line width in pixels
y Has *
there been
line yet?
n
Figure 7 The flowchart of the algorithmWe want to detect short circuits between the two equipotential areas. The inputs
of the analogic CNN algorithm are the two production layers of a PCB and the marker
images to define the two objects belonging to two different equipotential nodes. In the
first step by the algorithm the images are converted into black & white ones. We start a
wave from the marker image to reconstruct the layout elements belonging to this node.
The tracks of the different signals can be found by a wave. The waves arise on the marker
image but the form of the waves follows the tracks of the current production layer by
using “recall.tem”. (Figure 8)
The input images are the marker and the production layer images. By using the
recall template, we can build up a complete net defined on the marker image.
INPUT STATE
ORIGINAL MARKER
IMAGE (LAYER) Recall.tem IMAGE
(some iterations)
OUTPUT
INTERMEDIATE
RESULT
INPUT STATE
Recall.tem
(some iterations)
OUTPUT
RESULT
Figure 8 The operation of the “recall.tem” template
The 5th step by the same algorithm is used for the other production image and the
erosion template to remove the tracks from the reconstructed equipotential net. (Figure
11) The number of the iterations is directly proportional to the linear size of the images.Figure 9 The marker image Figure 10 The top layer
From the pads (Figure 11.) that we found on the top layer, we start the waves on
the bottom layer. (Figure 12.)
Figure 11 The top layer after erosion Figure 12 The bottom layer
Figure 13 The bottom layer after erosion Figure 14 The top layer
If we subtract the image (n-1)th from the image nth and get a white image, then we
do not have to run this intermediate algorithm. (Figure 15.)*
Logical AND
function between
image n-1
and image n.
Back to recall y
Are there
black objects?
n
Figure 15 Comparison of the n- th and (n-1) th image
When we build up the selected signal, the total pads of the signal on the image can
be seen.
Next we download the reference image into a platform. It is a black&white image
and includes some pads of the different signals (e.g. VDD, VSS).
We shall compare the two images of the pads by using the logic AND function. If
we get several pads on the result image, it means that there is at least one short-circuit on
one of the production layers.
4. Some real life examples
Experimental setup and image acquisition
The experimental system of layout error detection can be seen in Figure 16. A
standard HP ScanJet 3C was used as an input unit for Printed Circuit Boards or for
artwork films.PC
SCANNER
CNN-UM
Artwork film Drilled PCB CNN platform
Figure 16 The experimental environment
The image of the drilled PCB is gray-scale one therefore we have to run a
“treshold” template to convert the gray-scale image to a black&white one (corresponding
to the interconnection and the isolation areas). To get a good quality input for our
analogic CNN algorithms the proper scanning parameters (resolution, number of gray
levels, etc.) have to be set. For example the minimal wire-width or minimal separation
have to be covered by 2-3 pixels by using the proper resolution parameter of the scanner.
The proper alignment of the scanned images can be achieved by using the algorithm
defined on Figure 2.
The analogic CNN algorithms to detect the layout errors can be run either on software
simulator part of the ALADDIN System or on 20*22 CNN-UM chip [13] a 64*64 CNN-
UM chip [14] using the CNN platform.
Current experience on Misalignment Error Detection
We can see the picture of a drilled PCB in Figure 17 and the artwork film in Figure
18. The size of the example is 314*302 pixels. The critical snapshots of the proposed
analogic CNN algorithm are shown. We can see the wrong artwork film in Figure 18. The
errors have to be detected on this layout.Figure 17 Drilled PCB picture Figure 18 The Drilled PCB with
fitted artwork film
In Figure 19 we can see the result, after logical AND operation of the artwork film
and drilled PCB. A kind of size classification problem is solved here. If the two pictures do
not overlap fully, then we get this image. These are not errors because the difference
between the two layers is very small. We do not want to deal with small errors and the
“smkiller.tem” template is used for removing one-pixel-objects, see Figure 20.
Figure 21 shows the result, i.e. the real errors to be detected.
Figure 19 Logical AND between two pictures Figure 20 The result after
“smkiller” template
To increase the size of the real errors the dilatation template was used for a few
times. The result can been seen in Figure 21.Figure 21 The result after dilatation
Current experience on Short Circuit Detection
In this example we want to detect the short-circuit between the VDD and VSS.
We can see the top in Figure 22 and the bottom layer in Figure 23. On the latter layer
there is a short circuit which we would not detect by the previous approach [1] because
even a correct connection may cause this error. The size of the test image is 176*144
pixels. The line width is one pixel and the thicker lines are two-pixel-wide.
Figure 22 Top layer Figure 23 Bottom layer
The marker image can be seen in Figure 24. The whole VDD signal is built up from
the marker image on the TOP layer. (Figure 25)Figure 24 Marker image Figure 25 The intermediate top
layer after some iterations
From the pads of Figure 25 we start the waves on the bottom layer. With this step
we get some additional pads from which we can start some waves. (Figure 26) We can see
the additional pads and the VDD signal on the top layer. (Figure 27)
Figure 26 The intermediate Figure 27 The intermediate top
bottom layer layer after some iterations
In Figures 27 and 28 we can see the VDD and VSS signals as well as the pads.
(Figure 28)
Figure 28 The intermediate Figure 29 The intermediate top
bottom layer layer after some iterations
The reference image can be seen in Figure 30. The reference image and the
resulting image are compared by logic AND function. If there are some pads (at least 2)on the result image, then an error exists on one of the production layers. (Figure 31) It
means that there is a short circuit between the VDD and VSS signals.
If there are more than two pads on the reference image, then we can detect the
short-circuits among several signals.
Figure 30 The reference image Figure 31 The result image
We compared the running times of ALADDIN software simulator and the different
CNN-UM (Table 1).
It is important to stress that the running time of the layout error detection
algorithm, as far as the area is fully covered by the CNN-UM chip, is independent of the
image size and depends on the PCB technology only (wire and pad sizes, etc.).
Naturally, the running time depends on the size of the image if this image size is
larger than the CNN-UM chip. The size of the previously presented example is 314*302
or 176*144 pixels. The time requirement of these analogic CNN algorithms are given in
Table 1.
In our layout error detection algorithm the errors could be detected by using two
layers of production technology and in this respect, this application is different from the
previously published one.
Algorithms ALADDIN ALADDIN ALADDIN
Software with a 20*22 with a 64*64
Simulator on a CNN-UM CNN-UM
PENTIUM
466 MHz
Misalignment 9.28 sec 52 msec 22 msec
error detection
Short-circuit 105 sec N/A 90 msec *
detection
Table 1 The running times of the algorithm on the simulator and on the different CNN-
UM (* The running time of the algorithm’s core is 30 msec by using 64*64 CNN-UM.)
Our layout error detection algorithms were tested on real life examples of a PCB
production company, and regarding these examples the algorithms detected 100 % oferrors. Testing our algorithms on a large number of problems will be done in the near
future and based on the experience, a detailed statistical analysis can be made.
5. CONCLUSIONS
The templates used in these layout error detection algorithms are stable, due to
symmetric “A” templates. The analogic CNN algorithms were tested not only on
ALADDIN Software Simulator but they were implemented on a 20*22 binary input/binary
output CNNUM chip, a 64*64 analog input/analog output CNNUM as well. It is
supposed that in the analogic CNN algorithm the track width of a marked signal is smaller
than the pads of the selected signal. If we start some waves from several pads of the
selected signal, then the running time is smaller.
It is an important question how our solution refers in price/performance to the best
AOI systems. Our analogic CNN algorithms can process (by using a 64*64 CNN-UM)
4*106 – 0.3*106 pixels/s and the best traditional system works at an order of magnitude
higher speed [8] but our solution is at least two order of magnitude cheaper.
On the other hand, our algorithms were tested by using a general purpose
CNN-UM development system [12] as a complex hardware software environment of a
CNN-UM chip.
In the near future the speed of our solution will be at least two order of magnitude
higher by using 128*128 CNN-UM chip [23] and by using a more advanced interface [24]
to the host PC.
5. Acknowledgements
The helpful comments of Prof. Tamás Roska, László Kék and Tamás Bezák are
kindly acknowledged.
REFERENCES
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