PROGRAM ETS 2021 26th IEEE European Test Symposium May 24-28, 2021 - Belgium - European Test Symposium 2021
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©Jan D’Hondt & Tourism Bruges ETS 2021 26th IEEE European Test Symposium May 24-28, 2021 - Belgium PROGRAM
Program Content Foreword 2 Committees 4 Keynotes 10 Program at a Glance 14 Detailed Program 17 Monday 17 Tuesday 24 Wednesday 30 Thursday 39 Panel 40 Special Sessions 42 Embedded Tutorials 55 Industry Sessions 58 Vendor Sessions 63 Virtual Exhibitions 71 Test Spring School 84 Fringe Workshops 87 Fringe meetings 89 Social Activities 90 Conference Sponsors, Organizers & Media Partners 93 Corporate Supporters 94 1
Foreword The IEEE European Test Symposium (ETS) (www.ieee-ets.org) is Europe’s premier forum dedicated to presenting and discussing scientific results, emerging ideas, hot topics, and new trends, industrial case studies and applications in the area of electronic-based circuits and system testing, reliability, safety, security and validation. ETS’21 is the 26th edition and takes place from May 24th to May 27th, 2021. It is organized jointly by KU Leuven and imec, which co-sponsor the event together with the IEEE Council on Electronic Design Automation (CEDA). The original plan was to organize ETS in the heart of beautiful historic Bruges, Belgium (www.visitbruges.be), but the COVID-19 pandemic forced us to go virtual with the 2021 edition too. Yet, the organizing team strives to keep the spirit of ETS alive in the online edition, by organizing an event with live sessions and many opportunities for online networking and peer interaction among attendees and presenters. This virtual edition also provides a chance to attend each conference talk as video-on- demand for a full month after the above dates, in addition to a simu-live event with great interaction opportunities through live chat and video-conferencing facilities. We are proud to have received a high number of scientific paper submissions from 29 countries from all around the world. In the review and selection process, each submitted paper received on average five written expert reviews, based on which the Technical Program Committee (TPC) at its online meeting recommended to accept 25 papers for full presentation and 15 papers for poster presentation at the ETS’21 event. After the event, the Award Committee will select the ETS’21 Best Paper based on the reviewers’ comments, the quality of the video presentation, the follow-up online discussions and the ratings provided by the attendees. The Best Paper award will be handed out during the opening ceremony of ETS’22. In addition to the high-quality scientific paper presentations, the ETS’21 program offers 4 exciting keynote addresses, 4 special sessions and 3 one-hour embedded tutorials, covering a wide variety of established and emerging topics: from test standards to hardware security, reliability and test methods, from the testing of emerging (e.g. quantum) computing devices to the use of photonics for security primitives and novel approaches towards electronic system testing. The full program can be found on https://ets2021.eu. For young researchers, the PhD Forum and the Doctoral Thesis Contest provide opportunities at the beginning and at the end of their PhD studies, respectively, to get in touch with professionals from industry and academia. ETS’21 also includes an excellent industrial track with scientific talks given by renowned industrials, discussing the main challenges faced by today’s electronic testing industry. The vendor sessions present cutting-edge technology and product developments, and an online exposition area is available for vendors to advertise their products and to have live interaction with potential customers from both academia and industry. 2
Last but not least, a special effort has been done to make the event enjoyable from the social perspective as well, despite the virtual nature of this year’s edition: the implementation of a unique quiz dedicated to the test community, where all attendees are invited to participate both as individual and in teams, aiming to further reinforce the community bonds within the ETS community. ETS is the cornerstone event of the European Test Week, which also includes the Test Spring School (TSS) and the Fringe Workshops. TSS precedes the symposium from May 17th to May 24th, 2021. The focus topic for this year’s TSS edition is “Robustness in new computing paradigms and technologies”. For the first time, the TSS tutorial lectures, given by world renowned experts in the field, will also be available as video-on-demand to all attendees of ETS’21. As last part of the program offering, the Fringe Workshops will take place immediately after the ETS’21 symposium on May 28th, 2021. Three workshops will be organized in parallel: 1) the SURREALIST Workshop on SecURity, REliAbiLity, test, prIvacy, Safety and Trust of Future Devices; 2) the AI-TREATS Workshop on AI hardware: Test, REliAbility and Security; and 3) the TAAA Workshop on International Test Access, Automation and Adoption. ETS’21 is the result of the hard and voluntary work of many dedicated volunteers involved in the many technical and organizational activities. We wholeheartedly thank each and every one of them for their significant effort to put together this edition of ETS. The entire committee and the full final program can be found on the conference website: https://ets2021.eu. We also thank all authors who submitted their work to ETS’21, all presenters and all virtual attendees for their participation. We thank the KU Leuven Conferences and Events Office for logistic arrangements. We also thank the IEEE Council on Electronic Design Automation (CEDA) and the IEEE Computer Society Test Technology Technical Council (TTTC) for their continued financial respectively technical sponsorship of the event. We are particularly grateful to the many ETS’21 corporate supporters for their financial contribution and for their trust and constant support to ETS, making the ETS’21 program offering possible at very affordable registration rates. Although we cannot offer attendees the physical experience of savouring Bruges, we do invite everyone to visit the city and Flanders (www.visitflanders.com) in the near future, and in the meantime to fully enjoy the outstanding technical and social ETS’21 program that we have put together to savour online. Leuven, March 16, 2021 Georges Gielen & Michele Stucchi ETS’21 General co-Chairs Elena-Ioana Vătăjelu ETS’21 Program Chair 3
Organizing Committee General Chairs Program Chair Georges Gielen (BE) Elena-Ioana Vătăjelu (FR) Michele Stucchi (BE) General Vice Chairs Program Vice Chair Salvador Manich (ES) Salvador Mir (FR) Rosa Rodríguez-Montañés (ES) Finance Chair Ferenc Fodor (BE) Fringe Workshops Chairs Erik Larsson (SE), Ilia Polian (DE), Daniel Tille (DE) Local-Arrangements Chair Kristien Van Crombrugge (BE) Virtual Conference Chairs Lembit Jürimägi (EE), Stefano Di Carlo (IT) Industrial-Relations Chairs Erik Jan Marinissen (BE), Hans Manhaeve (BE) Publication Chair Mottaqiallah Taouil (NL) Review Chair Giorgio di Natale (FR) PhD Forum Chairs Liviu Miclea (RO), Ernesto Sanchez (IT) Awards Chairs Sybille Hellebrand (DE), Matteo Sonza Reorda (IT) McCluskey Doctoral Thesis Award Chairs Alberto Bosio (FR), Alessandro Savino (IT) 4
Publicity Chairs Jhon Gomez (BE), Mehdi Tahoori (DE) Web Chair Nektar Xama (BE) Test Spring School Chairs Sybille Hellebrand (DE), Haralampos Stratigopoulos (FR) CTCQ Organization Chairs Erik Jan Marinissen (BE), Alicja Lesniewska (BE), Rafal Madgziak (BE), Francesco Lorenzelli (BE), Pietro Inglese (FR) Regional Liaisons Krishnendu Chakrabarty (US), Sameer Chillarige (IN), Junling Huang (CN), Shi-Yu Huang (TW), Shuichi Kameyama (JP), Huawei Li (CN), Nicola Nicolici(CA), Sungju Park (KR), Paolo Rech (BR) 5
Program Committee Program Chair Embedded Tutorials Chair Elena-Ioana Vătăjelu (FR) Hans Martin Von Staudt (DE) Program Vice Chair Industry Sessions Chairs Salvador Mir (FR) Wim Dobbelaere (BE), Steve Sunter (CA) Topic Chairs Alberto Bosio (FR), Stefano Di Special Sessions Chairs Carlo (IT), Goerschwin Fey (DE), Said Hamdioui (NL), Martin Keim (US), Erik Nele Mentens (BE) Larsson (SE), Gildas Leger (ES), Regis Leveugle (FR), Teresa Panel Chairs McLaurin (US), Mottaqiallah Jeff Rearick (US), Taouil (NL) Mehdi Tahoori (DE) Program Committee Members Juergen Alt Marie-Lise Flottes Husasm Amrouch Frank Frederick Lorena Anghel Valentin Gherman Davide Appello Patrick Girard Luz Balado Dimitris Gizopoulos Manuel Barragan Said Hamdioui *Bernd Becker *Pete Harrod Mounir Benabdenbi Gurgen Harutyunyan Paolo Bernardi *Sybille Hellebrand Leticia Bolzani Poehls Stefan Holst Gabriele Boschi Jiun-Lang Huang Ramon Canal Ke Huang Riccardo Cantoro Sebastian M. Huhn John Carulli Maksim Jenihhin Luca Cassano Artur Jutman Krishnendu Chakrabarty Naghmeh Karimi *Giorgio Di Natale Ramesh Karri Wim J Dobbelaere Rene Krenz-Baath Rolf Drechsler Bram Kruseman Stephan Eggersgluess Prashant M Kulkarni Piet Engelke Wolfgang Kunz 6
Huawei Li Alessandro Savino Yiorgos Makris Mario Schölzel Erik Jan Marinissen Melanie Schilinsky Peter Maxwell Juergen Schloeffel Nele Mentens Christoph Scholl *Maria K Michael Johanna Sepulveda Liviu C. Miclea Muhammad Shafique Salvador Mir Matteo Sonza Reorda Grzegorz Mrugalski *Haralampos G. Stratigopoulos Maria Mushtaq Fei Su Zainalabedin Navabi Stephen Sunter Stelios N Neophytou Daniel Tille Nicola Nicolici Yiorgos E. Tsiatouhas Alex Orailoglu Jerzy Tyszer *Zebo Peng Elena Ioana Vatajelu Ilia Polian Federico Venini. Jean-Michel Portal Ingrid Verbauwhede Mihalis E Psarakis Massimo Violante Jaan Raik Arnaud Virazel Janusz Rajski Hans Martin Von Staudt Paolo Rech Xiaoqing Wen Rosa Rodriguez-Montanes *Hans-Joachim Wunderlich Ernesto Sanchez Vladimir Zivkovic Matthias Sauer * ETS 21 Review Companions for Topic Chairs 7
Steering Committee Matteo Sonza Reorda (IT) – Chair Lorena Anghel (FR) Rolf Drechsler (DE) Giorgio Di Natale (FR) Stephan Eggersglüß (DE) Georges Gielen (BE) Patrick Girard (FR) Said Hamdioui (NL) Pete Harrod (UK) Sybille Hellebrand (DE) Artur Jurman (EE) Hans Manhaeve (BE) Salvador Manich (ES) Erik Jan Marinissen (BE) Maria K. Michael (CY) Liviu Miclea (RO) Zebo Peng (SE) Jaan Raik (EE) Rosa Rodriguez (ES) Haralampos Stratigopoulos (FR) Michele Stucchi (BE) Mehdi Tahoori (DE) Elena-Ioana Vatajelu (FR) Hans-Joachim Wunderlich (DE) Yervant Zorian (US) 8
CONVERGING TECHNOLOGIES A D VA N C I N G THE FUTURE Advantest is the leading manufacturer of automatic test and measurement equipment used in the design and production of semiconductors. Founded in Tokyo in 1954, Advantest is a global company with facilities around the world and a commitment to sustainable practices and social responsibility: Our Products Today’s complex semiconductors, whether powering technologies such as 5G, Internet of Things (IoT), artificial intelligence (AI), autonomous driving, machine learning or others, perform innumerable tasks at breathtaking speeds. Each of these chips goes through numerous, complex tests at every phase of the development and production process, before being incorporated into their end use device. Advantest’s modular test platforms make it easy to test a wide variety of devices, enable speedy and flexible support for customer business. These systems ensure full device functionality while reducing device and manufacturing costs. Shaping the World of Tomorrow Boeblingen, Germany hosts one of Advantest’s most important research and development centers. Here, latest technologies in the field of semiconductor test are developed for global semiconductor manufacturers. Environmental Social Government (ESG) for Sustainability In line with our Corporate Mission, we at Advantest aim to achieve sustainable growth and mid/long-term improvement of corporate value by promoting ESG management. Through the development of test solutions that will help to achieve sustainable development goals, Advantest seeks to continuously provide safety, security, and comfort to people worldwide, and to contribute to the planet's sustainable future. Career and Jobs Whether you are experienced or a young professional, find out about the interesting job offers on our career page. We also offer dual study and training programs to give you a successful start to your career. www.advantest.com
Keynotes Building and Validating Advanced 1 Quantum Systems Oliver Dial - IBM TJ Watson Research Center Quantum computing is on the verge of dramatically changing the landscape of what is and is not computable. As numerous academic and industrial groups pursue this challenge with a variety of different physical underpinnings, the question of how do we test a quantum system becomes essential, both to provide metrics to guide research and development, and to answer comparative questions between dramatically different technologies. Beginning with a brief introduction to quantum computing in general and superconducting qubits in specific, I will introduce metrics and measurements that we use to perform physical, component-level and system-level testing of quantum systems with specific references back to the underlying physical hardware as. Finally, I'll discuss where it appears the field will be in a few years time and the new characterization challenges that will introduce. Short Bio Oliver Dial is the technical lead for quantum hardware in IBM Quantum, with a research focus on novel and high performance multi-qubit systems. At IBM he has worked on qubit coherence and gates in both 2D and 3D Transmon systems. He joined IBM in 2012 having first entered the field of quantum computing as a post-doc at Harvard by demonstrating the first two-qubit gate between semiconductor singlet-triplet qubits and providing benchmark charge noise data for these systems. Dr. Dial received his PhD from MIT in 2007 for research in two-dimensional electron and hole systems. 10
From Wearables to Ingestibles and 2 Invisibles: Disruptive New Health Devices and Their Path to Maturity & the Market Chris Van Hoof - imec Over the past decade wearables have had increasing impact in the health domain and predominantly in the cardiovascular field. Their relatively fast success was certainly aided by the presence of traditional vital sign or holter monitors which could act as so-called predicate devices. To make a similar difference in other medical fields, such as gastro-intestinal disorders and metabolic health, radically new device concepts are needed, such as ingestible sensors. These new device concepts do not have existing med tech counterpart devices to be compared to and this poses both regulatory and acceptance hurdles. Furthermore, apart from the hardware challenges, these devices will often rely on digital twin models. Acceptance of such AI algorithms is a compound challenge to their regulatory approval and acceptance. In this keynote, several of these new sensors and concepts will be presented as well as their expected path (and the hurdles) taking them from first demonstration to clinical studies and to market. Short Bio Chris Van Hoof Vice President R&D at imec and general manager of the OnePlanet Research Center in Gelderland. Chris believes preventive health, personalised nutrition, sustainable food production and reduced waste are essential enablers of improving our world for the generations to come. And he is convinced that technology (hardware and AI) are key tools to make that happen. After receiving a PhD in Electrical Engineering from the University of Leuven in 1992, Chris has held positions as manager and director at imec in highly diverse fields spanning technology, circuits, systems, data and applications. Apart from delivering industry-relevant innovative solutions to customers, his work also resulted in five startups (four in the healthcare domain). He is also full professor at the University of Leuven and imec Fellow. 11
A Cambrian Explosion in Electronic 3 System Testing is Dead Ahead Subhasish Mitra - Stanford University Today's test technologies mostly serve 20th-century manufacturing needs of silicon CMOS chips. In this new decade, testing is going to change radically, driven by several factors: (a) Testing must grow beyond manufacturing defects to address robustness that end-users really care about: design bugs, reliability, and security. (b) Today's test methods cannot meet the increasing levels of thoroughness demanded by future systems --- from (self- driving) cars to the cloud. (c) Beyond-silicon NanoSystems create new testing challenges. These factors create golden opportunities for new "System-Driven" test approaches that address the above seemingly diverse problems at seemingly diverse scales. Testing will then become an essential 21st-century system feature rather than a cost burden defined by the constraints of 20th-century chip manufacturing. Short Bio Subhasish Mitra is Professor of EE and CS at Stanford University. He also holds the Carnot Chair of Excellence in NanoSystems at CEA-LETI (France),. Prof. Mitra has consulted for many companies including Cisco, Google, Intel, Samsung and Xilinx. His research ranges across Robust Computing, NanoSystems, Electronic Design Automation (EDA), and Neurosciences. Prof. Mitra has created key approaches for circuit failure prediction, on-line diagnostics, QED system validation, soft error resilience, and X-Compact test compression. His X-Compact approach has proven essential for cost-effective manufacturing and high-quality testing of almost all 21st-century systems, enabling billions of dollars in cost savings. With students and collaborators, he demonstrated the first carbon nanotube computer and the first 3D NanoSystem with computation immersed in data storage. Prof. Mitra's honors include the ACM SIGDA/IEEE CEDA Newton Technical Impact Award in EDA (test of time honor), the Semiconductor Research Corporation’s Technical Excellence Award, the Intel Achievement Award (Intel’s highest honor), and the US Presidential Early Career Award. He is an ACM Fellow and an IEEE Fellow. 12
Secure hardware design: starting 4 from the roots of trust Ingrid Verbauwhede - KU Leuven What is "hardware" security? The network designer relies on the security of the router box. The software developer relies on the TPM (Trusted Platform Module). The circuit designer worries about side-channel attacks.At the same time, electronics shrink: sensor nodes, IOT devics, smart devices are becoming more and more available. Adding security and cryptography to these often very resource constraint devices is a challenge. This presentation will focus on Physically Unclonable Functions and True Random Number Generators, two roots of trust, and their security testing. Short Bio Dr. Ir. Ingrid Verbauwhede is a Professor in the research group COSIC of the Electrical Engineering Department of the KU Leuven. She is also adjunct professor at UCLA, USA. She received her PhD degree from the KU Leuven and was a post-doctoral researcher at UC Berkeley. At COSIC, she leads the secure embedded systems and hardware group. She is a Member of IACR and a fellow of IEEE. She was elected as member of the Royal Flemish Academy of Belgium for Science and the Arts in 2011. She is a recipient of an ERC Advanced Grant in 2016 and received the IEEE 2017 Computer Society Technical Achievement Award. She is a pioneer in the field of efficient and secure implementations of cryptographic algorithms on many different platforms: ASIC, FPGA, embedded, cloud. With her research she bridges the gaps between electronics, the mathematics of cryptography and the security of trusted computing, including Physically Unclonable Functions and True Random Number Generators. Her group owns and operates an advanced electronic security evaluation lab. She is the author and co-author of more than 300 publications at conferences, journals, book chapters and books. 13
Program at a Glance UTC+2 Monday Tuesday 14h00 - Opening 14h30 Keynote 2 - From wearables to ingestibles and invisibles: disruptive new health 14h30 - devices and their path to maturity & the 15h00 Keynote 1 - Building and Validating market - Chris Van Hoof Advanced Quantum Systems - Oliver Dial 15h00 - IS3 - 15h30 Analog SP1 - S5 - Memory Defect Exploring and Test & 15h30 - Simulatio Comparing Reliability 16h00 IS1 - n In IEEE P1687.1 Diagnosing Industry S1- Test and IEEE Failing Generation 1687 Mixed-Signal Modeling and 16h00 - Ics E. J. Implementatio Break + Vendor Booths 16h30 McCluskey n of NON-TAP Best Doctoral Interfaces Thesis Award at ETS 16h30 - Break + Vendor Booths 17h00 S6 - Sensors Vendor and Session 2 Monitors for - IS2 - SP2 - safety and OpenTAP Solutions 17h00 - Emerging security Tutorial For 17h30 Computing Preventing Devices: S2 - AMS- Latent Challenges RF Defects and From 17h30 - Opportunities Causing Break + Vendor Booths 18h00 for Test and System Reliability Faults 18h00 - Vendor Vendor S7 - 18h30 S3 - S4 - Hardware Session 1 - S8 - Session 3 - Miscelaneou Standards security Test Quantum Wafer Probe s Equipment Technology 18h30 - 19h00 19h00 - 19h30 Author Interview session + Gathertown Author Interview session + Gathertown 19h30 - 20h00 14
Wednesday Thursday UTC+2 SP3 - Keynote 4 - Vendor 14h00 - Recent Secure Session 4 14h30 Advances Hardware - S9 - on Design: Innovativ Miscelaneous Photonic Starting from e Test Physical the Roots of Approach 14h30 - Unclonable Trust-Ingrid es 15h00 Functions, Verbauwhede ET3 - ET2 - 15h00 - ET1 - Speed- Analog Security 15h30 path Test and Panel Validation, Automati Resilience (ends at Silicon on – An of 16:10) Debug, Delay Overview Quantum 15h30 - Test of IEEE Computing 16h00 P1687.2 Closing Session 16h00 - Break + Vendor Booths (starts at 16h30 16:10) 16h30 - Keynote 3 - A Cambrian Explosion in 17h00 Electronic System Testing is Dead Ahead - Subhasish Mitra Global Test 17h00 - Community 17h30 Quiz (GTCQ) 17h30 - PhD Forum & Posters & McCluskey 18h00 Sward 18h00 - 18h30 SP4 - Security, 18h30 - S10 - Non- Reliability Vendor 19h00 Volatile and Test Session 5 Memories Aspects of - EDA the RISC-V 19h00 - Ecosystem 19h30 19h30 - Author Interview session + Gathertown 20h00 https://ets2021.eu/program/ 15
Detailed Program Monday, May 24th *14:00 - Opening session 14:30 Keynote 1 Building and Validating Advanced Quantum 14:30 - Systems 15:30 Oliver Dial - IBM Quantum Moderator: Georges Gielen (KU Leuven – Belgium) Session 1 - Test generation Chair: Daniel Tille Speeding Up Cell-Aware Library Characterization by Preceding Simulation with Structural Analysis, 15:30 - Francesco LORENZELLI (University of Bologna - Italy), 15:50 Zhan GAO (IMEC - Belgium), Joe SWENTON, Santosh MALAGI (Cadence Design Systems - United States), Erik Jan MARINISSEN (IMEC - Belgium) (CS) Testing Embedded Toggle Pattern Generation Through On-Chip IR Drop Monitoring, Kazuki MONTA (Graduate School of Science, Technology and Innovation, Kobe University, Kobe, Japan - Japan), 15:50 - Leonidas KATSELAS (Aristotle University of 16:10 Thessaloniki - Greece), Ferenc FODOR (IMEC - Belgium), Alkis HATZOPOULOS (Aristotle University of Thessaloniki - Greece), Makoto NAGATA (Kobe University - Japan), Erik Jan MARINISSEN (IMEC - Belgium) Best paper candidate * All times in UTC+2 17
Unsupervised Learning in Test Generation for Digital 16:10 - Integrated Circuits, Soham ROY, Spencer MILLICAN, 16:30 Vishwani AGRAWAL (Auburn University - United States) Special Session 1 - Exploring and Comparing IEEE 15:30 - P1687.1 and IEEE 1687 Modeling and 16:30 Implementation of NON-TAP Interfaces Organisers: Martin Keim & Jeff Rearick Speakers: Hans-Martin von Staudt (Dialog Semiconductor, Kirchheim unter Teck, Germany) Jeff Rearick, Advanced Micro Devices (USA) Michele Portolan (Univ Grenoble Alpes, CNRS, Grenoble INP1, TIMA, France) Martin Keim (Siemens Digital Industries Software, USA) Industry Session 1 - Diagnosing Failing Mixed-Signal Chairs: Haralampos Stratigopoulos & Stephen Sunter Diagnosis of SAR-ADC INL/DNL Failures using Capacitor Matching Techniques, Stefano ROGGI, 15:30 – Peter BOGNER, Rocco CALABRO, Josef NIEDERL, 15:50 Dario VAGNI, Andreas FUGGER (Infineon Technologies – Austria), Jaafar MEJRI, Ralf ARNOLD (Infineon Technologies – Germany) Defect Oriented Diagnostic For Analog: Why 15:50 – Building a Defect Oriented Test Database Matters, Jo 16:10 GUNNES (NXP Semiconductors – Netherlands) Automated Analog Fault Simulators: Application to 16:10 – Failure Analysis, Tommaso MELIS (ST 16:30 Microelectronics – Italy) 16:30 - Break & Vendor Booths 17:00 18
Session 2 - AMS-RF Chairs: Gildas Leger & Artur Pogiel Exploration of a digital-based solution for the generation of 2.4GHz OQPSK test stimuli, Thibault VAYSSADE, Mouhamad CHEHAITLY (Univ. Montpellier, 17:00 - CNRS, LIRMM - France), Florence AZAIS (Univ. 17:20 Montpellier, CNRS - France), Laurent LATORRE (LIRMM - France), Francois LEFEVRE (NXP, FR - France) BIST-Assisted Analog Fault Diagnosis, Antonios PAVLIDIS (Sorbonne Univ., CNRS, LIP6 - France), Eric 17:20 - FAEHN (STM - France), Marie-Minerve LOUERAT 17:40 (Sorbonne Université - CNRS - France), Haralampos STRATIGOPOULOS (Sorbonne Univ., CNRS, LIP6 - France) Analysis and mitigation of timing inaccuracies in high-frequency on-chip sinusoidal signal generators 17:40 - based on harmonic cancellation, Ankush MAMGAIN, 18:00 Manuel BARRAGAN, Salvador MIR (TIMA Laboratory - France) Special Session 2 - Emerging Computing Devices: Challenges and Opportunities for Test and Reliability Organizer: Alberto Bosio Quantum Accelerators: from quantum application to 17:00 – simulator execution, Koen Bertels (Qbee and 17:20 University of Porto – Portugal) Dependability for AI Hardware Architectures, 17:20 – Muhammad Shafique (New York University Abu Dhabi – 17:40 UAE) Approximation-Based Fully Reliable TMR Alternative 17:40 – for Safety-Critical Applications, Marcello Traiola 18:00 (Ecole Centrale de Lyon – France) 19
Industry Session 2 - Solutions for preventing latent defects from causing system faults Chairs: Riccardo Cantoro & Mark Zwolinski From Screening Latent Defects Towards Auto Correction, Ronny VANHOOREN, Anthony COYETTE, 17:00 – Wim DOBBELAERE (ON Semiconductor – Belgium) 17:20 Jhon GOMEZ, Nektar XAMA, Georges GIELEN (KU Leuven – Belgium) Automotive Quality Requirements and Industrial 17:20 – Volume Production: Zero Defect Meets the Real 17:40 World, Ralf MONTINO, Christian THUM (Elmos Semiconductor) Techniques to Mitigate Latent Defects in the Digital 17:40 – World, Jeff REARICK (Advanced Micro Devices – 18:00 United States) Session 3 – Standards Chairs: Michele Portolan & Pete Harrod System-Level Access to On-Chip Instruments, Erik 18:00 - LARSSON, Shashi Kiran GANGARAJU, Prathamesh 18:20 MURALI (Lund University - Sweden) (CS) Applying IEEE 1838 to the 3DIC Design Trishul - 18:20 - A Case Study, Teresa MCLAURIN (ARM - United 18:40 States), Frank FREDERICK, Saurabh SINHA, Heath PERRY, Shawn HUNG (Arm - United States) (P) A Tutorial of How to Ensure High Automotive 18:40 - Microcontroller Quality, Ralf ARNOLD (Infineon 18:45 Technologies - Germany) (P) A 3DIC interconnect interface test and repair 18:45 - scheme based on Hybrid IEEE1838 Die Wrapper 18:50 Register and BIST circuit, Changming CUI, Junlin HUANG (Hisilicon - China) 20
Session 4 - Hardware Security Chairs: Giorgio Di Natale & Adam Cron Compact Protection Codes for protecting memory arrays from malicious data and address 18:00 - manipulations, Gilad DAR, Avihay GRIGIAC, Yagel 18:20 ASHKENAZI, David PELED (Bar-Ilan University - Israel), Menachem GOLDZWEIG (biu university - Israel), Yoav WEIZMAN, Osnat KEREN (Bar-Ilan University - Israel) RHAT: Efficient RowHammer-Aware Test for Modern 18:20 - DRAM Modules, Mohammad FARMANI, Mark 18:40 TEHRANIPOOR, Fahim RAHMAN (University of Florida - United States) (P) Opacity preserving Countermeasure using Finite State Machines against Differential Scan Attacks, Sk. 18:40 - Subidh ALI (IIT Bhilai - India), Yogendra SAO (Indian 18:45 Institute of Technology Bhilai - India), Santosh BISWAS (IIT Bhilai - India) (P) Trustworthy computing on untrustworthy and 18:45 - Trojan-infected on-chip interconnects, Heba SALEM, 18:50 Nigel TOPHAM (The University of Edinburgh - United Kingdom) (P) Chill Out: Freezing Attacks on Capacitors and DC/DC Converters, Obi NNOROM JR, Jalil MORRIS 18:50 - (Yale University - United States), Ilias GIECHASKIEL 18:55 (Independent Researcher - United Kingdom), Jakub SZEFER (Yale University - United States) (P) Transit-Guard: An OS-based Defense Mechanism Against Transient Execution Attacks, Maria 18:55 - MUSHTAQ, David NOVO (LIRMM - France), Florent 19:00 BRUGUIER, Pascal BENOIT (Universite de Montpellier - France), Muhammad Khurram BHATTI (Information Technology University - Pakistan) 21
Vendor Session 1: Test Equipment Moderators: Bram Kruseman & Hans Manhaeve Solving Test Challenges of State-of-the-Art Power 18:00 - Devices, Thomas KOEHLER, Dennis KEOGH, Chuck 18:20 CARLINE (Teradyne – United States) Keysight’s Massively Parallel Board Test System, 18:20 - Sivakumar VIJAYAKUMAR (Keysight Technologies - 18:40 Singapore) Improving Reliability Insights Through Cost- 18:40 - Effective, Flexible Parallel WLR Systems, Joris 19:00 DONDERS (NI – Belgium) https://ets2021.eu/monday/ 22
Tuesday, May 25th Keynote 2 From wearables to ingestibles and invisibles: disruptive new health devices and their path to *14:00 - maturity & the market 15:00 Chris Van Hoof - Vice-President R&D, imec, Leuven, Belgium Moderator: Michele Stucchi (imec – Leuven, Belgium) Session 5 - Memory Test and Reliability Chairs: Martin Keim & Arnaud Virazel Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs, Guilherme CARDOSO MEDEIROS (TU Delft - Netherlands), Moritz FIEBACK, 15:00 - Anteneh GEBREGIORGIS (Delft University of 15:20 Technology - Netherlands), Leticia Bolzani POEHLS (Catholic University of Rio Grande do Sul - Brazil), Mottaqiallah TAOUIL, Said HAMDIOUI (Delft University of Technology - Netherlands) Run Time Management of Faulty Data Caches, 15:20 - Michail MAVROPOULOS (University of Patras - 15:40 Greece), Georgios KERAMIDAS (Aristotle University - Greece), Dimitris NIKOLOS (U. Patras - Greece) ESD-PCM: Constructing Reliable Super Dense Phase 15:40 - Change Memory Under Write Disturbance, Wenke 16:00 JIN, Siqi LU, Xiaojun CAI (Shandong University - China) Best paper candidate * All times in UTC+2 24
Industry Session 3 - Analog Defect Simulation in Industry Chairs: Hans Martin Von Staudt & Martin Andraud Analog Defect Coverage – History, Status Now and 15:00 – Challenges Still Ahead of Us, Dieter HAERLE, Jaafar 15:20 MEJRI, Thierry VERNET (Infineon Technologies – Germany) Analog Defect Simulators – Initial Successes and Remaining Challenges, Anthony COYETTE, Wim 15:20 – DOBBELAERE, Ronny VANHOOREN (ON 15:40 Semiconductor – Belgium) Jhon GOMEZ, Nektar XAMA, Georges GIELEN (KU Leuven – Belgium) An Effective Iterative Method to Improve Mixed- 15:40 – Signal Manufacturing Test Quality, Fred FU, Yifan GE 16:00 (HiSilicon – China) 16:00 - Break & Vendor Booths 16:30 Session 6 - Sensors and Monitors for safety and security Chairs: Paolo Bernardi & Liviu Miclea (CS) A Plug and Play Digital ABIST Controller for Analog Sensors in Secure Devices, Sebastien 15:00 - LAPEYRE (INVIA - France), Marie-lise FLOTTES, Bruno 15:20 ROUZEYRE, Arnaud VIRAZEL (LIRMM - France), Nicolas VALETTE, Marc MERANDAT (INVIA - France) (HT) Designing Recurrent Neural Networks for Monitoring Embedded Devices, Fin Hendrik 15:20 - BAHNSEN (Hamburg University of Technology – 15:40 Germany), Jan KAISER (Deutsches Elektronen- Synchrotron DESY – Germany), Goerschwin FEY (TU Hamburg – Germany) https://ets2021.eu/tuesday/ 25
(CS) SafeSU: an Extended Statistics Unit for Multicore Timing Interference, Guillem CABO, Francisco BAS, Ruben LORENZO, David TRILLA, Sergi 15:40 - ALCAIDE, Moretó MIQUEL, Carles HERNANDEZ 16:00 (Barcelona Supercomputing Center – Spain), Jaume ABELLA (Barcelona Supercomputing Center (BSC-CNS) – Spain) Vendor Session 2: OpenTAP Tutorial Moderators: Erik Larsson & Jouke Verbree Going Open (Source), The Future Of Test & 16:30 - Measurement Automation, Jeff DRALLA (Keysight 16:50 Technologies - United States), Michael DIEUDONNE (Keysight Technologies – Belgium) 16:50 - OpenTAP: The Open Source Path To Effortless 17:10 Automation, Brennen DIRENZO (Keysight Technologies - United States) 17:10 - OpenTAP Enables Massively Parallel Board Tester 17:30 on Keysight System, Sivakumar VIJAYAKUMAR (Keysight Technologies - Singapore) 15:00 - McCluskey Award 17:30 Leaky Hardware: Modeling and Exploiting McC1 Imperfections in Embedded Devices, Ilias GIECHASKIEL (University of Oxford) Testing STT-MRAM: Manufacturing Defects, Fault McC2 Models, and Test Solutions, Lizhou WU (Delft University of Technology) Security Techniques for Test Infrastructures, McC3 Emanuele VALEA (LIRMM – CNRS) 26
Efficient Post-Silicon Debug Framework for Future McC4 Many-Core Systems, Sidhartha Sankar ROUT (Indraprastha Institute of Information Technology) Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM McC5 Timing Parameter Margins, Jeremie KIM (Carnegie Mellon University) Assessing Dependability of ML-driven Systems, McC6 Saurabh Jha (University of Illinois at Urbana- Champaign) Effective techniques for systems validation and McC7 security, Aleksa Damljanovic (Politecnico di Torino) 17:30 - Break & Vendor Booths 18:00 Session 7 – Miscelaneous Chairs: Marcello Traiola & Ernesto Sanchez Arithmetic Circuit Correction by Adding Optimized 18:00 - Correctors Based on Groebner Basis Computation, 18:20 Negar AGHAPOUR SABBAGH, Bijan ALIZADEH (University of Tehran - Iran, Islamic Republic of) NeuroScrub: Mitigating Retention Failures Using Approximate Scrubbing in Neuromorphic Fabric 18:20 - Based on Resistive Memories, Soyed Tuhin AHMED, 18:40 Michael HEFENBROCK, Christopher MÜNCH, Mehdi TAHOORI (Karlsruhe Institute of Technology – Germany) https://ets2021.eu/tuesday/ 27
(P) Hierarchical Fault Simulation of Deep Neural Networks on Multi-Core Systems, Masoomeh KARAMI, Mohammad-Hashem HAGHBAYAN 18:40 - (University of Turku - Finland), Masoumeh EBRAHIMI 18:45 (KTH - Sweden), Antonio MIELE (Politecnico di Milano - Italy), Hannu TENHUNEN (KTH - Sweden), Juha PLOSILA (University of Turku - Finland) (P) Analyzing the Impact of Approximate Adders on 18:45 - the Reliability of FPGA Accelerators, Ioannis 18:50 TSOUNIS, Athanasios PAPADIMITRIOU, Mihalis PSARAKIS (University of Piraeus - Greece) (P) Online Testing of a Row-Stationary Convolution 18:50 - Accelerator, Mohammad Rasoul ROSHANSHAH, 18:55 Katayoon BASHARKHAH, Zainalabedin NAVABI (University of Tehran - Iran, Islamic Republic of) Session 8 – Quantum Chair(s): Salvador Mir & Swaroop Gosh Test Data-Driven Machine Learning Models for 18:00 - Reliable Quantum Circuit Output, Vedika 18:20 SARAVANAN, Samah SAEED (City College of New York, City University of New York) ArsoNISQ: Analyzing Quantum Algorithms on Near- Term Architectures, Sebastian BRANDHOFER 18:20 - (University of Stuttgart), Simon DEVITT (University of 18:40 Technology Sydney), Ilia POLIAN (University of Stuttgart) (P) Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum Dot Cellular Automata, Syed 18:40 - Farah NAZ, Ambika Prasad SHAH (Indian Institute of 18:45 Technology Jammu), Suhaib AHMED (Baba Ghulam Shah Badshah University), Patrick GIRARD (LIRMM), Michael WALTL (Institute for Microelectronics, TU Wien) 28
Vendor Session 3: Wafer Probe Technology Moderators: Jeroen De Coster & Stojan Kanev Improving Parametric Test Quality and Efficiency 18:00 - With XP5 Probe Material, Joe Mai (JEM Europe - 18:20 France), Romain LAVEVILLE, Guillaume DUTERTRE (ST Microelectronic - France) Flexible Wafer-Level Optical Probing Solutions: 18:20 - Meeting the Cycle-Time Demands of Engineering to 18:40 High-Volume Silicon Photonics Manufacturing, Dan Rishavy (FormFactor - United States) Fine-Pitch WLCSP Spring Probe Pointing Accuracy 18:40 - and Wobble, Bert Brost (Technoprobe America – United 19:00 States) 29
Wednesday, May 26th Session 9 – Miscelaneous Chairs: Mihalis Psarakis & Maria Mushtaq (CS) Exploiting Active Learning for Microcontroller Performance Prediction, Nicolò BELLARMINO, Riccardo CANTORO (Politecnico di Torino – Italy), Martin HUCH (Infineon Technologies AG – Germany), *14:00 - Tobias KILIAN (Infineon Technologies AG, Technical 14:20 University of Munich – Germany), Raffaele MARTONE (Politecnico di Torino – Italy), Ulf SCHLICHTMANN (TUM – Germany), Giovanni SQUILLERO (Politecnico di Torino – Italy) (CS) An Ordinal Optimization-Based Approach To Die Distribution Estimation For Massively Multi-site Testing Validation, Isaac BRUCE, Praise FARAYOLA 14:20 - (Iowa State University - United States), Shravan 14:40 CHAGANTI, Abalhassan SHEIKH, Abdullah OBAIDI (Texas Instruments - United States), Srivaths RAVI (Texas Instruments - India), Degang CHEN (Iowa State University - United States) (P) Automatic Inspection for Wafer Defect Detection with Unsupervised Clustering Techniques, Katherine Shu-Min LI (National Sun Yat-sen University - Taiwan), Leon Li-Yang CHEN (NXP Semiconductors Taiwan Ltd. 14:40 - - Taiwan), Peter Yi-Yu LIAO, Ken Chau-Cheung CHENG 14:45 (NXP Semiconductor Taiwan Ltd. - Taiwan), Sying-Jyan WANG (National Chung-Hsing University - Taiwan), Andrew Yi-Ann HUANG, Leon CHOU, Nova Cheng-Yen TSAI, Chen-Shiun LEE (NXP Semiconductor Taiwan Ltd. - Taiwan), Gus Chang-Hung HAN (National Chung- Best paper candidate * All times in UTC+2 30
Hsing University - Taiwan), Jwu E CHEN (NCU – Taiwan), Hsing-Chung LIANG (Chung Yuan Christian University - Taiwan), Chun-Lung HSU (Industrial Technology Research Institute - Taiwan) (P) TDMS Test Scheduler: An Integrated Framework 14:45 - for Test Scheduling of DVFS-based SoCs with 14:50 multiple voltage islands, Fotios VARTZIOTIS (University of Ioannina - Greece) (P) GPU-based ATPG System by Scaling Memory 14:50 - Usage and Reducing Data Transfer, Hua-Ren LI, 14:55 Hsing-Chung LIANG (Chung Yuan Christian University - Taiwan) Special Session 3 - Recent Advances on Photonic Physical Unclonable Functions Organizer: Fabio Pavanello Can Optical PUFs Save Us? A Subjective 14:00 – Perspective, Ulrich Rührmair (University of Connecticut 14:20 – USA) 14:20 – Physical Keys in Silicon Photonics, Amy Foster (John 14:40 Hopkins University – USA) Photonic Physical Unclonable Functions based on scattering random optical media: Optical Speckle 14:40 – response / key generation and its relation to the 15:00 structured light input properties, Dimitris Syvridis (University of Athens – Greece) Vendor Session 4: Innovative Test Approaches Moderators: Erik Bury & Andrea Ganio Precision Static ADC Test: Using Cost-Optimized 14:00 - Sinusoidal Methodologies on Advantest V93000, 14:20 Matthias Werner (Advantest Europe - Germany) 31
14:20 - ISOVU Technology - A Radically New Probing 14:40 Solution, Sven De Coster (CN Rood - Belgium) How To Keep Testing of New Generation Silicon 14:40 - Affordable in The Future, Armando FERNANDEZ, 15:00 (Salland Test Technology Center - the Netherlands) 15:00 - Embedded Tutorials 16:00 Speed-path Validation, Silicon Debug, Delay Test, Embedded Speakers: Arani SINHA (Intel); Sandip RAY (U Florida) Tutorial 1 Chair: Patrick GIRARD (LIRMM/CNRS – France) Security and Resilience of Quantum Computing, Embedded Speaker: Swaroop GHOSH (Pennsylvania State Tutorial 2 University) Chair: Samah SAEED (The City College of New York – USA) Analog Test Automation – An Overview of IEEE P1687.2, Speakers: Hans Martin von STAUDT (Dialog Embedded Semiconductor), Steve SUNTER (Mentor a Siemens Tutorial 3 Business) Chair: Haralampos STRATIGOPOULOS (Sorbonne University – France) 16:00 - Break & Vendor Booths 16:30 Keynote 3 A Cambrian Explosion in Electronic System Testing 16:30 - is Dead Ahead 17:30 Subhasish MITRA – Professor, Stanford University Moderator: Georges Gielen (KU Leuven – Belgium) 17:30 - PhD Forum & Posters Session & MCCluskey Award 18:30 ARCHITECTURAL-SPACE EXPLORATION OF ENERGY-EFFICIENT APPROXIMATE ARITHMETIC UNITS FOR ERROR-TOLERANT APPLICATIONS, PF-1 Haroon WARIS, Chenghua WANG, Weiqiang LIU (College of EIE, Nanjing University of Aeronautics and Astronautics, China) 32
HOW SGX SECURITY CLAIMS MEET REAL LIFE SCENARIOS, Valentin MARTINOLI (Univ. Grenoble PF-2 Alpes, TIMA & Thales, France), Regis LEVEUGLE (Univ. Grenoble Alpes, TIMA, France), Yannick TEGLIA (Thales, France) BRIEF OVERVIEW ON LOGIC IN MEMORY SOLUTIONS, Pietro INGLESE, Elena Ioana VATAJELU, PF-3 Giorgio DI NATALE (Univ. Grenoble Alpes, CNRS - TIMA, France) NEURON FAULT TOLERANCE IN SPIKING NEURAL NETWORKS, Theofilos SPYROU (Sorbonne Universite, CNRS, LIP6, France), Sarah ALI EL-SAYED (Sorbonne Universite, CNRS, LIP6, France), Engin AFACAN (Sorbonne Universite, CNRS, LIP6, France), Luis Alejandro CAMUNAS MESA (Instituto de PF-4 Microelectronica de Sevilla, CSIC y Universidad de Sevilla, Spain), bernabe LINARES-BARRANCO (Instituto de Microelectronica de Sevilla, CSIC y Universidad de Sevilla, Spain), Haralampos STRATIGOPOULOS (Sorbonne Universite, CNRS, LIP6, France) TOWARDS RELIABILITY OF SNNS: DEFECT MODELING AND SIMULATION ON STT-MRAM CELL, PF-5 Salah DADDINOUNOU, Elena Ioana VATAJELU (Univ. Grenoble Alpes, CNRS - TIMA, France) NOVEL ATTACK AND DEFENSE STRATEGIES FOR ENHANCED LOGIC LOCKING SECURITY, Lilas PF-6 ALRAHIS, Hani SALEH (System on Chip Research Center (SOCC), Khalifa University, U.A.E.) A Tutorial of How to Ensure High Automotive P1 Microcontroller Quality, Ralf ARNOLD (Infineon Technologies - Germany) A 3DIC interconnect interface test and repair scheme based on Hybrid IEEE1838 Die Wrapper Register and P2 BIST circuit, Changming CUI, Junlin HUANG (Hisilicon - China) 33
Opacity preserving Countermeasure using Finite State Machines against Differential Scan Attacks, Sk. P3 Subidh ALI (IIT Bhilai - India), Yogendra SAO (Indian Institute of Technology Bhilai - India), Santosh BISWAS (IIT Bhilai - India) Trustworthy computing on untrustworthy and Trojan-infected on-chip interconnects, Heba SALEM, P4 Nigel TOPHAM (The University of Edinburgh - United Kingdom) Transit-Guard: An OS-based Defense Mechanism Against Transient Execution Attacks, Maria MUSHTAQ, David NOVO (LIRMM - France), Florent P5 BRUGUIER, Pascal BENOIT (Universite de Montpellier - France), Muhammad Khurram BHATTI (Information Technology University - Pakistan) Chill Out: Freezing Attacks on Capacitors and DC/DC Converters, Obi NNOROM JR, Jalil MORRIS P6 (Yale University - United States), Ilias GIECHASKIEL (Independent Researcher - United Kingdom), Jakub SZEFER (Yale University - United States) Hierarchical Fault Simulation of Deep Neural Networks on Multi-Core Systems, Masoomeh KARAMI, Mohammad-Hashem HAGHBAYAN P7 (University of Turku - Finland), Masoumeh EBRAHIMI (KTH - Sweden), Antonio MIELE (Politecnico di Milano - Italy), Hannu TENHUNEN (KTH - Sweden), Juha PLOSILA (University of Turku - Finland) Analyzing the Impact of Approximate Adders on the Reliability of FPGA Accelerators, Ioannis TSOUNIS, P8 Athanasios PAPADIMITRIOU, Mihalis PSARAKIS (University of Piraeus - Greece) Online Testing of a Row-Stationary Convolution Accelerator, Mohammad Rasoul ROSHANSHAH, P9 Katayoon BASHARKHAH, Zainalabedin NAVABI (University of Tehran - Iran, Islamic Republic of) 34
Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum Dot Cellular Automata, Syed Farah NAZ, Ambika Prasad SHAH (Indian Institute of P10 Technology Jammu), Suhaib AHMED (Baba Ghulam Shah Badshah University), Patrick GIRARD (LIRMM), Michael WALTL (Institute for Microelectronics, TU Wien) Automatic Inspection for Wafer Defect Detection with Unsupervised Clustering Techniques, Katherine Shu-Min LI (National Sun Yat-sen University - Taiwan), Leon Li-Yang CHEN (NXP Semiconductors Taiwan Ltd. - Taiwan), Peter Yi-Yu LIAO, Ken Chau-Cheung CHENG (NXP Semiconductor Taiwan Ltd. - Taiwan), Sying-Jyan WANG (National Chung-Hsing University - Taiwan), P11 Andrew Yi-Ann HUANG, Leon CHOU, Nova Cheng-Yen TSAI, Chen-Shiun LEE (NXP Semiconductor Taiwan Ltd. - Taiwan), Gus Chang-Hung HAN (National Chung- Hsing University - Taiwan), Jwu E CHEN (NCU - Taiwan), Hsing-Chung LIANG (Chung Yuan Christian University - Taiwan), Chun-Lung HSU (Industrial Technology Research Institute - Taiwan) TDMS Test Scheduler: An Integrated Framework for Test Scheduling of DVFS-based SoCs with multiple P12 voltage islands, Fotios VARTZIOTIS (University of Ioannina - Greece) GPU-based ATPG System by Scaling Memory Usage and Reducing Data Transfer, Hua-Ren LI, Hsing- P13 Chung LIANG (Chung Yuan Christian University - Taiwan) Leaky Hardware: Modeling and Exploiting MC1 Imperfections in Embedded Devices, Ilias GIECHASKIEL (University of Oxford) Testing STT-MRAM: Manufacturing Defects, Fault MC2 Models, and Test Solutions, Lizhou WU (Delft University of Technology) Security Techniques for Test Infrastructures, MC3 Emanuele VALEA (LIRMM – CNRS) 35
Efficient Post-Silicon Debug Framework for Future MC4 Many-Core Systems, Sidhartha Sankar ROUT (Indraprastha Institute of Information Technology) Improving DRAM Performance, Security, and Reliability by Understanding and Exploiting DRAM MC5 Timing Parameter Margins, Jeremie KIM (Carnegie Mellon University) Assessing Dependability of ML-driven Systems, MC6 Saurabh Jha (University of Illinois at Urbana- Champaign) Effective techniques for systems validation and MC7 security, Aleksa Damljanovic (Politecnico di Torino) Session 10 - Non-Volatile Memories Chairs: Rosa Rodriguez Intermittent Undefined State Fault in RRAM, Moritz FIEBACK (Delft University of Technology - Netherlands), Guilherme CARDOSO MEDEIROS (TU Delft - 18:30 - Netherlands), Anteneh GEBREGIORGIS (Delft 18:50 University of Technology - Netherlands), Hassen AZIZA (IM2NP - Aix-Marseille Université - France), Mottaqiallah TAOUIL, Said HAMDIOUI (Delft University of Technology - Netherlands) MBIST-based Trim Adjustment to Compensate Thermal Behavior of MRAM, Christopher MÜNCH 18:50 - (Karlsruhe Institute of Technology - Germany), Jongsin 19:10 YUN (Mentor - United States), Martin KEIM (Mentor, a Siemens Business - United States), Mehdi TAHOORI (Karlsruhe Institute of Technology - Germany) Convolutional Compaction-Based MRAM Fault Diagnosis, Jerzy TYSZER (Poznan University of Technology - Poland), Martin KEIM (Mentor, a Siemens 19:10 - Business - United States), Artur POGIEL (Mentor 19:30 Graphics - Poland), Janusz RAJSKI (Mentor, A Siemens Business - United States), Bartosz GRZELAK (Poznan University of Technology - Poland) 36
Special Session 4 - Security, Reliability and Test Aspects of the RISC-V Ecosystem Organizer: Francesco Regazoni 18:30 – How RISC-V can help in security research, Frank K. 18:45 Gürkaynak (ETH Zurich – Switzerland) Thwarting Differential Power Analysis Attacks on 18:45 – RISCV processors, Michael Hutter, Elke De Mulder, 19:00 Helena Handschuh (Rambus – USA) SW-only and HW/SW support for diverse 19:00 – redundancy for high-integrity applications, Jaume 19:15 Abella (Barcelona Supercomputing Center – Spain) Towards Bridging the Gap between System-level and Structural Test for the RISC-V Platform, Nourhan 19:15 – Elhamawy, Jens Anders, Steffen Becker, Matthias 19:30 Sauer, Stefan Wagner, Ilia Polian (University of Stuttgart and Advantest – Germany) Vendor Session 5: EDA Moderators: Andreas Glowatz & Tom Waayers Highly Accurate and Scalable Failure Diagnosis for 18:30 - Large Designs with Complex DfT Architectures, 18:50 Sameer CHILLARIGE (Cadence Design Systems - India) Siemens Presents Tessent Streaming Scan Network 18:50 - (SSN): No-Compromise DfT, Geir EIDE (Siemens EDA 19:10 - United States) Using Data Analytics to Debug and Trace Multi-Chip Module (MCM) Test Failures During the 19:10 - Manufacturing Process for Reducing Overall Test 19:30 and Manufacturing Costs, Guy CORTEZ (Synopsys - United States) 37
Thursday, May 26th Keynote 3 Secure hardware design: starting from the roots of *14:00 - trust 15:00 Ingrid VERBAUWHEDE - KU Leuven Session Moderator: Michele Stucchi (imec – Leuven, Belgium) Panel - Design and Manufacturing Technology of Advanced Multi-Die Packages on the ‘Slope of Enlightenment’: Where Is 3D-Test? Moderator: Jan Vardaman – President (TechSearch International, Inc. – USA) Panelist: Dave Armstrong – Director of Business 15:00 - Development (Advantest – USA) 16:10 Harry Chen – Scientist, IC Testing (Mediatek – Taiwan) Sandeep K. Goel – Academician/Deputy Director (TSMC – USA) Yu Huang – EDA Chief Architect (HiSilicon – China) Teresa McLaurin – Fellow and Senior Director of DFT Architecture (arm – USA) 16:10 - Closing Session 16:30 Global Test Community Quiz (GTCQ) 16:30 - The first Global Test Community Quiz (GTCQ) 2021 is a 18:00 free “must-attend” social event for everyone who considers him/herself member of the world-wide electronics test community. * All times in UTC+2 39
Panel Design and Manufacturing Technology of Advanced Multi-Die Packages on the ‘Slope of Enlightenment’: Where Is 3D-Test? TUESDAY, MAY 27TH, 2021, 15:00 – 16:10 UTC+2 Moderator: Jan Vardaman – President (TechSearch International, Inc. – Austin, TX, USA) Panelists: Dave Armstrong – Director of Business Development (Advantest – Lafayette, CO, USA) Harry Chen – Scientist, IC Testing (MediaTek – Hsinchu, Taiwan) Sandeep K. Goel – Academician/Deputy Director (TSMC – San Jose, CA, USA) Yu Huang – EDA Chief Architect (HiSilicon – Shenzhen, China) Teresa McLaurin – Fellow and Senior Director of DFT Architecture (Arm – Austin, TX, USA) Organizers: Michele Stucchi – Principal Member of Technical Staff (imec – Leuven, Belgium), Erik Jan Marinissen – Scientific Director (imec – Leuven, Belgium) When a new manufacturing IC technology starts getting the interest of test engineers, that is usually the sign of imminent introduction of a new product in the market. Since the first paper on testing 3D-stacked integrated circuits (3D- SICs) interconnected by through-silicon vias was published by Lewis & Lee at ITC-2007, ‘advanced’ multi-die packages have gone through the subsequent stages of a fresh hype cycle (*), and we would currently position them at the end of the “slope of enlightenment”. During these years, 3D-SIC technology and design approaches, as well as target applications, have evolved quite a bit. Therefore, this is the appropriate moment to review, with a panel of experts, and YOU, the audience, where we, as the test community, stand now in 3D-test. 40
Special Sessions Special Session 1: Exploring and Comparing IEEE P1687.1 and IEEE 1687 Modeling and Implementation of NON-TAP Interfaces MONDAY, MAY 24TH, 2021, 15:30 – 16:30 UTC+2 Organizers: Martin KEIM, Jeff REARICK In this special session, the contributors explore and differentiate IEEE 1687 from IEEE 1687.1. It starts with exploring and comparing the solutions based on privately extended IEEE 1687 and an equivalent solution based on IEEE P1687.1. Both use the IJTAG call-back feature, something rarely used. The former in an ad-hock way, the latter in a structured way as described in IEEE P1687.1, where the call-back is central. In a similar way, this methodology extends from IEEE P1687.1 into IEEE P2654. We close with a presentation of working examples of key features of an IEEE P1687.1 implementation, including such call-backs. In summary, the industry is moving forward with answers to today’s problems based on today’s solutions, anticipating and implementing future IEEE P1687.1. This underlines the purpose, critical demand, and practicality of IEEE P1687.1 before it is even completely defined. Speakers: Hans-Martin von Staudt (Dialog Semiconductor, Kirchheim unter Teck, Germany) Jeff Rearick (Advanced Micro Devices, USA) Michele Portolan (Univ Grenoble Alpes, CNRS, Grenoble INP1, TIMA, France) Martin Keim (Siemens Digital Industries Software, USA) https://ets2021.eu/special-sessions/ 42
Special Session 2: Emerging Computing Devices: Challenges and Opportunities for Test and Reliability MONDAY, MAY 24TH, 2021, 17:00 – 18:00 UTC+2 Organizer: Alberto BOSIO Energy and power efficiency is undoubtedly one of the major driving forces of current computer industry, which is relevant for supercomputers on the one hand, as well as for small portable personal electronics and sensors on the other hand. Today’s computing devices are based on the CMOS technology that, thanks to the Moore’s Law, allowed performance increase coupled with fabrication cost reduction. However, pushed by the forecasted end of Moore’s law, several emerging technologies (e.g., nanodevices, optical computing, quantum computing) are candidates to either replace or co-exist with the de facto standard CMOS technology. Moreover, technology is not the only root cause for the inefficiency of computing devices. In fact, the computing architecture itself is changing moving from the computation- to data- oriented paradigms in order to break the well-known “memory wall”. Those new technologies and computing paradigms will not only change the way we used to design and program our computers, but also the way we used to test them to provide the required quality and reliability. Unfortunately this is not a straightforward process. For example, Artificial Intelligence applications shown relevant resilience properties to faults, meaning that the testing strongly depends on the application behavior rather than on the hardware structure. On the other hand, Approximate Computing even takes benefit from the wrong behavior of the hardware to reduce overheads. The consequence is that we may not have to test for all the possible faults but only for the “critical” ones. Finally, for some technologies such as quantum computing the concept of “behavior” is probabilistic therefore clearly impacting the concept of test. 17:00 – Quantum Accelerators: from quantum application to 17:20 simulator execution Koen Bertels (Qbee and University of Porto – Portugal) Abstract: The talk will focus on the different layers that a quantum accelerator needs to have to be fully operational, both in development of quantum applications up to the execution on a quantum simulator to validate and verify the quality of the qubits. The challenges in quantum computing go from the 43
highest algorithmic level up to the low-level electronics to control the analogue phenomena that are used in quantum computing. Speaker bio: Koen Bertels current scientific research focuses on quantum computing and more specifically on the definition and implementation of a scalable quantum micro- and system architecture. He was a professor at Delft University of Technology working on the quantum topics. He is now at the University of Porto in Portugal and has created a company called QBee.eu. His work still involves specifying what the micro-architectural support is for the control of the quantum instructions and how the quantum accelerator is connected and integrated in a larger system design where classical logic is combined with quantum logic. The main approach focuses more on quantum accelerators and the full-stack definition that the QCA lab has defined and developed. In this context, we have defined a programming language, OpenQL, a template for the micro-architecture and the QBeeSim simulator platform to execute any quantum logic that can be defined. 17:20 – Dependability for AI Hardware Architectures 17:40 Muhammad Shafique (New York University Abu Dhabi – UAE) Abstract: Deep Learning (DL) has emerged as the state-of-the- art for many Artificial Intelligence (AI) applications. Now-a-days models trained using DL are being used/research for safety- critical applications where even a single failure can lead to catastrophic results. Therefore, it is vital to ensure the robustness of DNNs against a wide range of dependability threats that include hardware- induced threats such as soft errors, aging, and manufacturing defects. Traditional fault- mitigation techniques that are based on redundancy (e.g., Dual Modular Redundancy (DMR) and Triple Modular Redundancy (TMR)) are not effective for DNN-based applications due to their huge overheads arising from redundant hardware/execution of compute-intensive DNNs and synchronization issues. Other techniques such as Instruction Duplication (ID) and use of Error- Correcting Codes (ECC) also pose similar issues that lead to noticeable degradation in system’s performance and power- /energy-efficiency. To address this, alternate techniques need to be developed that exploit the intrinsic characteristics of DNNs to boost their fault -resilience at low cost. These techniques should be integrated in the current state-of-the-art systems without affecting their performance-/power-efficiency. Towards this, this talk will provides an overview of different techniques for 44
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