Highlights of the CSC/GEM upgrade workshop at Texas A&M - Manuel Franco Sevilla UC Santa Barbara - CERN Indico
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Highlights of the
CSC/GEM upgrade
workshop at Texas A&M
Manuel Franco Sevilla
UC Santa Barbara
17th April 2018
General Muon Meeting (GMM) during CMS week
The workshop
CSC/GEM upgrade workshop 8-11 April 2018, Texas A&M
➡ https://indico.cern.ch/event/712513/timetable/?view=standard
➡ As usual, fantastic organization by Alexei and rest of Texas A&M folks
✴ Food brought in every day, tasty and efficient way of working during lunch!
About 40 attendants, 23 in College Station
Focus on open questions and CSC/GEM synergies
CSC upgrade GEM upgrade
1. Majority of installation in 2019-20 1. Installation in 2022-23 (GE2/1) and 2024-25 (ME0)
2. Focus on answers to narrow questions 2. Focus on R&D steps after broad discussions
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 2
CSC upgrade in LS2
LS2 upgrade overview
Darien Wood
Phase 2
ME234/1 chambers Need to upgrade all on-chamber electronics in ME234/1 to cope
Copper
with increased rate/latency
Fiber CSC ➡ No access to endcaps in LS3 → on-chamber upgrade in LS2
Wires ➡ Also upgrade LV, HV due to higher currents
42×
LVDB5
AFEBs
DCFEBs are on critical path
LS2 Strips
ALCT 5×DCFEBs ➡ 3 month contingency, 2 months already used waiting for financial approval
2017 2018 2019 2020
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
LS2 OTMB ODMB Opt. fibers
LVDB5
DCFEB (+) Start MEX/1 installation
UXC On-chamber
DCFEB (-) Today EDR
USC
ALCT-LX150T
New FED
ALCT-LX100
board LV system
HV system Off-chamber
Trigger DAQ OTMB
LS3
Color code Design Engin. Prototype Pre-production Production Float Install. & Commiss.
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 4
Focus on open questions
Darien Wood
On the first day, laid out main open questions for CSC
CSC questions for LS2 CSC questions for LS3
1. Powering down GBTx in xDCFEB/ALCT? 8. Which FPGA for the ODMB?
2. Duplex connection on the xDCFEB’s VTRx? 9. Which optical transmitter for the ODMB?
3. Replace Finisars in DCFEBs with VTTx on adaptor board? 10. Reuse ODMBv1 in ME34/1?
4. OTMB copper inputs needed? 11. Which ATCA board for FED?
5. How many spare fibers? 12. How to partition DAQ system?
6. GE2/1 → OTMB connection? 13. Program DCFEBs/ALCTs from ODMB instead of FED?
7. Increase OTMB bandwidth with direct connection to EMTF? 14. Do we want/need 2-way ODMB/FED communication?
15. Can improved LCT resolution improve triggering?
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 5
xDCFEB
Ben Bylsma
First prototype of xDCFEB fully tested in January
➡ No problem with fabrication
PROMs: 2×XCF32P, XCF08P
➡ Small design fixes needed
➡ Some bad BGA connections VTTx
✴ Mix of leaded and lead-free VTRx
✴ Will move to lead-free
Second prototype ready to
be submitted
PO delays ate 2/3 month
➡
contingency
Q1 ➡ Added ability to power off GBTx
✴ Needs to be tested GBTx
Q2 ➡ Discussed duplex fibers for VTRx
✴ No need to read registers
✴ Need to test that simplex fully OK
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 6
Adaptor board for DCFEBs
Ben Bylsma
1.5% of Finisar opt. transceiver in current DCFEBs have failed in 2 years
➡ Some correlation with luminosity (5x higher incidence in ME1/1a than ME1/1b, 2017 > 2016)
Q3 Ben presented options to replace Finisars with the VTTx
DCFEB Finisars VTTx
xDCFEB
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 7
Adaptor board for DCFEBs: options
1” beyond edge of DCFEB
Q3 Both options allow access to VTTx screws, provide 2.5V to VTTx Ben Bylsma
Ben Bylsma -- GEM/CSC Forward Muon Workshop
Option 1 Advantages
Epoxy QSS/QTS connectors on ➡ Connectors designed for high
DCFEB. Adaptor board plugs into speed diff. signals
connectors ➡ Maintains DCFEB envelope
Ben Bylsma -- GEM/CSC Forward Muon Workshop
1” beyond
DCFEB edge
Advantages
Option 2 ➡ Implementation straight forward
Placed directly on ➡ Simple design/fewer components
DCFEB, holes aligned
➡ Connection to cooling cover
s barremove
remove
ured by guide
Screws accessible
solder
solder
solder
ard-to-board
orner of the
ccessible
Voted to go ahead and build option 2 prototypes to test difficulty of implementation
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 8
EB
le
o
‣
ALCT-LX150T/LX100
Two transmitters running at 3.2 Gbps each provide optical DAQ link
ALCT Mezzanine Upgrade ✦ Utilizes
✦ 8b10b
CERN radiation-hard VTTX twin-transmitter
encoding, 80 MHz commercial reference clock
ALCT ALCT-LX150T ALCT-LX100
Two new designs for LS2 installation:
New ALCT mezzanines LX150T LX100
LX100 Andrew Peck
108 LX150T for ME234/1
➡
LX150T ‣ LX100 boards have a smaller FPGA and reduced pinout
➡ 72 LX100 for ME1/1 with optics
216 LX100
‣ ➡ LX150T for have
boards ME123/2 without
larger FPGA optics
✦ Drops compatibility with ALCT672 boards to reduce cost and complexity
for large ALCT 672 boards (ME234/1)
✴ Jumper to GBTx turn off Q2
‣ GBTx chip provides
✦ Requires more IO pins + logic and ALCT 288 and EEPROM-less
384 boards programming and optical DAQ link
Most functionality
LX150T Test already
Results LX100
tested
✦ 4.8 GpbsTest
link, Results
with
‣ Two transmitters running at 3.2 Gbps each provide 4.48 Gbps of user
optical DAQ linkbandwidth
LX150T prototype received April
Card #1 6
✦ Utilizes
Voltages Check
CERN
PASS
radiation-hard
LX100 prototype
Card #2
VTTX
Supply Voltages
PASS
Card #3 • received March
Check
PASS
twin-transmitter
PASS
26
(after overhead,
Card #1
PASS PASS
w/ optional
Card #2 wide-frame
Card #3 ALCT
ALCTSpartan-6
ALCT
mode) Spartan-6Family
Spartan-6 Family
Family
✦ 8b10b encoding, 80 MHz commercial JTAG Program Utilizes CERN radiation
✦FPGA PASS hard
PASSVTRX transmitter/receiver
PASS
(images
(images
totoscale)
to scale)
JTAG Program FPGA PASS PASS PASS
reference clock (images scale)
EEPROM Program FPGA PASS EEPROM Program
PASS PASSFPGA PASS PASS PASS
✦ Plug-in optics will remain unstuffed in non-ME1/1 stations
Mezzanine ADC Voltage Self Check PASS Mezzanine
PASS Voltage Self Check
PASS PASS PASS PASS
Single Cable Loopback PASS Single Cable Loopback
PASS PASS PASS PASS PASSLX100
LX100 Delay Chip r/w PASS
EMU PhasePASS
PASS Delay Chip
IIr/wWorkshop PASS PASS PASS 3 9 April 2018
TMB Tx/Rx Scan PASS PASS TMB Tx/Rx PASS
Scan PASS PASS PASS
‣ ODMB
LX100
PRBS Test boards have work-in-progress
work-in-progress a smallerCTP7 FPGA and reduced
IBERT
work-in-progress PASS pinout
PASS PASS
Cosmics test @ 904 EEPROMless
work-in-progress work-in-progress Programming
work-in-progress work-in-progress work-in-progress work-in-progress
✦ Drops compatibility with FPGA
ALCT672
Elinks Test boards to reduce cost
work-in-progress and complexity
work-in-progress work-in-progress
+1.8V current = 0.2A
Cosmics test @ 904 work-in-progress work-in-progress work-in-progress
+3.3V current = 2.9A
‣ GBTx chip provides EEPROM-less programming and optical DAQ link
Will need to re-assign
EMU Phase II Workshop 9
some
w/ CMS firmware, LVDS
configured GBTx 9 April 2018
+1.8V current = 0.1A
outputs on LX100
✦ 4.8 Gpbs link, with 4.48
output Gbps
elinks of user
not running bandwidth
in firmware +3.3V current = 2.6A
➡ No new prototype
• (after needed
overhead, for this wide-frame
w/ optional 13 mode)
EMU Phase II Workshop 9 April 2018
✦ Utilizes
Manuel Franco Sevilla CERN radiation hard VTRX transmitter/receiver S6-LX150
Summary of CSC/GEM S6-LX150
S6-LX150
upgrade workshop S6-LX150T
S6-LX150T
S6-LX150T S6-LX100
S6-LX100
S6-LX100Slide 9
OTMBv2
OTMBv2s needed to read optical output of DCFEBs in ME234/1
➡ New voltage regulator and opt. transceiver (Firefly), otherwise same as OTMBv1
Agreed that legacy copper connectors can be removed Q4
➡ Would liberate front panel space for a new optical RX, if it is needed
In ME234/1, we need exactly 12 fibers Jason Gilmore
➡ 5 for DCFEB → OTMB
➡ 5 for DCFEB → ODMB
➡ 2 for ALCT-LX150T → ODMB
Agreed to use one 12-fiber bundle per chamber Q5
OTMB
➡ Split in peripheral crate into two MTP12s
➡ Will buy bundle of 4 bundles per PC
From
chamber
✴ One spare 12-fiber bundle every 3 chambers
ODMB
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 10GE2/1 → OTMB connection
Option 1: fiber from GE2/1 to ME2/1 chamber Jason Gilmore
Q6 ➡ Cheapest option, need to confirm that 7 fibers enough for GE2/1
➡ Rejected because of latency, routing complications
Option 2: use “Y” connector to patch bundles from GE2/1 and ME2/1
➡ Mechanically awkward, additional fiber interface, need to confirm that 7 fibers enough for GE2/1
➡ About $200 per chamber MTP12 for ODMB
From ME2/1
Firefly Ribbon Detail
From GE2/1
MTP12 for OTMB
Option 3: split firefly into two MTP12 connectors at the OTMB
➡ Requires front panel space, need to confirm that 7 fibers enough for GE2/1
➡ About $100 per chamber (to be confirmed)
If price and feasibility of
Option 4: add 2nd firefly RX on OTMB splitting Firefly into two
➡ Allows for 12 fibers from GE2/1 MTP12s is confirmed with
➡ About $260 per chamber Samtec, go with Option 3
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 11
J. Gilmore CMS Muon Upgrade Workshop at TAMU 7LV power
Power/disk present & future
Armando Lanaro
Doing the math for on-chamber and peripheral crate power consumption minimal
LS2 # Maratons # Maratons
ME1 (#108) Extra power needs/disk (3.6 kW) Upgrade
Upgraded electronics in Available power = 43.2kW On chamber +954 W
Present
YE1
ME234/1 will require Used power = ~25.4kW Off chamber power neutral 12 12
➡ 6-12 new Maratons e (used capacity) = 59% tot +954 W (+4%)
➡ 6-12 new OPFCs
ME2+ME3 (#108)
➡ New junction boxes On chamber +3521 W
➡ New LVDB5s
YE2 Available power = 28.8kW 8 10
Used power = ~18.2kW Off chamber +1145 W
e = 63% tot +4666 W (+26%)
ME4 (#54) 4 5
YE3
Available power = 14.4kW On chamber +1743 W
Used power = ~8.8kW Off chamber + 573 W
24 27
e = 61% tot +2316 W (+26%)
Total for 2 endcaps 48 54
7
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 12LS2 installation
k + GE1/1 installation drive LS2 endcap critical path
schedule
on to surface → storage → refurbishing → initial testing → long-term Refurbishment
(burn-in) → final testing → storage → reinsertion → commissioning
• SX5 area needs to be cleaned
David Morse u
LS2 schedule is being carefully optimized
surface work parallelized as much as ndpossible – Some boxes of skew-clear cab
➡ Recently were able to delay need-by date for 2 batch of xDCFEBs moved toTo do some unused
b904,
material
1. Design moved to trash
chamber-holding
LS2 schedule [days] tables in early summer
LS2 Workday 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 320 340 360 – Target end July
2. Clean up SX5 area for completel
e, beampipe extraction,
Openingetc.
emptied area
1st batch of 252 xDCFEBs
sequence needed by March 2019
ME-1/1 work
ME-1/1
now
SX5 now
ME+x/1 work
ME+234/1 DCFEBs moved to 2nd batch of 252 xDCFEBs
ME+234/1 and needed by October 2019
ALCT-LX150
ME+1/1
ME+1/1 work needed by June 2019
ME-234/1
ME-x/1 work
op 9 April 2018
Manuel Franco Sevilla
David Morse
Summary of CSC/GEM upgrade workshop
4 CSC/GEM Workshop 9 April 2018 David Morse
Slide 13Copper
Fiber CSC
Wires
42× LVDB5
AFEBs
LS2 Strips
CSC upgrade
OALCT-S6 5×DCFEBs
in LS3
LS2 OTMB ODMB
UXC
USC
New FED
board
Trigger DAQ
LS3
2017 2018 2019 2020 2021 2022 2023 2024 2025
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
ODMB Today PRR
FED system EDR
Color code Design Engin. Prototype Pre-production Production Float Install. & Commiss.Data rates at the HL-LHC
Nominal
Table extrapolation
5: Expected data rates for the is
CSCquadratic
system at the(proportional to luminosity
HL-LHC for the design ×
(L = 5 ⇥ 1034 cm L1
2
s 1 )rate)
➡ Reality
and probably
ultimate (L between
= 7.5 ⇥ 1034
cm 2 s linear
1 and quadratic
) luminosity scenarios. Bandwidth utilizations in red indicate safety
Manuel Franco Sevilla
factors Linear
✴ for triggered
lower than two, and muons,
in brownquadratic for random
safety factors coincidences
between two and three.
Linear extrapolation Quadratic extrapolation
L = 5 ⇥ 1034 cm 2
s 1
L = 7.5 ⇥ 1034 cm 2
s 1
L = 5 ⇥ 1034 cm 2
s 1
L = 7.5 ⇥ 1034 cm 2
s 1
Rate Link Util. Rate Link Util. Rate Link Util. Rate Link Util.
Chamber [Gb/s] [Gb/s] [%] [Gb/s] [Gb/s] [%] [Gb/s] [Gb/s] [%] [Gb/s] [Gb/s] [%]
ME1/1 0.9 1⇥1.6 67 1.3 1⇥1.6 100 4.3 1⇥1.6 333 9.6 1⇥1.6 749 ODMBs/DMBs in
ME2/1 0.6 1⇥1.6 44 0.9 1⇥1.6 66 2.8 1⇥1.6 221 6.4 1⇥1.6 498 ME1234/1 not able to
ME3/1 0.3 1⇥1.6 25 0.5 1⇥1.6 37 1.6 1⇥1.6 125 3.6 1⇥1.6 281 cope with data rates
ME4/1 0.3 1⇥1.6 25 0.5 1⇥1.6 37 1.6 1⇥1.6 123 3.5 1⇥1.6 276 expected at the HL-LHC
ME1/2 0.1 1⇥1.6 4 0.1 1⇥1.6 6 0.3 1⇥1.6 20 0.6 1⇥1.6 45
ME2/2 0.0 1⇥1.6 3 0.0 1⇥1.6 4 0.2 1⇥1.6 13 0.4 1⇥1.6 28
ME3/2 0.0 1⇥1.6 3 0.1 1⇥1.6 5 0.2 1⇥1.6 15 0.4 1⇥1.6 35
ME4/2 0.1 1⇥1.6 6 0.1 1⇥1.6 9 0.4 1⇥1.6 31 0.9 1⇥1.6 70
ME1/3 0.0 1⇥1.6 0 0.0 1⇥1.6 1 0.0 1⇥1.6 2 0.1 1⇥1.6 5
TOTAL 119 Gb/s 179 Gb/s 597 Gb/s 1,344 Gb/s CSC should be designed
for ultimate scenario
Aggressive, probable underestimation Conservative, in TDR Further discussion on Friday
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 15ODMB7 and ODMB5
Table 4: Expected data rates for the CSC system at the HL-LHC for the design (L = 5 ⇥ 1034 cm 2
s 1
) Manuel Franco Sevilla
and ultimate (L = 7.5 ⇥ 1034 cm 2
s 1
) luminosity scenarios. Bandwidth utilizations in red indicate safety
Need FPGA under $600-700 and 6.4-10 Gb/s links
factors lower than two, and in brown safety factors between two and three. L = 7.5 ⇥ 1034 cm
Option 1: Xilinx Artix-7
2 1
s
6.4 Gb/s links 10 Gb/s links 10 Gb/s links ➡ $294, limited to 6.4 Gb/s
900 fibers 720 fibers 900 fibers
Rate Link Util. Rate Link Util. Rate Link Util.
Option 2: Microsemi PolarFire
Chamber [Gb/s] [Gb/s] [%] [Gb/s] [Gb/s] [%] [Gb/s] [Gb/s] [%]
➡ $391, links at 10 Gb/s,
ME1/1 9.6 4 ⇥ 6.4 47 9.6 3 ⇥ 10 40 9.6 4 ⇥ 10 30 ➡ Requires significant R&D
ME2/1 6.4 3 ⇥ 6.4 42 6.4 2 ⇥ 10 40 6.4 3 ⇥ 10 27
Option 3: Artix-7 + lpGBT Q8
ME3/1 3.6 2 ⇥ 6.4 35 3.6 1 ⇥ 10 45 3.6 2 ⇥ 10 22
➡ $291, links at 10 Gb/s
ME4/1 3.5 2 ⇥ 6.4 35 3.5 1 ⇥ 10 44 3.5 2 ⇥ 10 22
➡ Depends on lpGBT schedule
ME1/2 0.6 1 ⇥ 1.6 45 0.6 1 ⇥ 1.6 45 0.6 1 ⇥ 1.6 45
➡ Thanks Evaldas! Meets all requirements,
ME2/2 0.4 1 ⇥ 1.6 28 0.4 1 ⇥ 1.6 28 0.4 1 ⇥ 1.6 28
decision in 2019
ME3/2 0.4 1 ⇥ 1.6 35 0.4 1 ⇥ 1.6 35 0.4 1 ⇥ 1.6 35
ME4/2 0.9 1 ⇥ 1.6 70 0.9 1 ⇥ 1.6 70 0.9 1 ⇥ 1.6 70 As opt. transceiver will use Q9
ME1/3 0.1 1 ⇥ 1.6 5 0.1 1 ⇥ 1.6 5 0.1 1 ⇥ 1.6 5 ➡ Firefly for DCFEBs/ALCT
Need to reduce overall data rates, improve ➡ VL+ for FED (if on time)
shielding, perhaps use a few ODMB5s
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 16New FED (backend)
Evaldas Juska
Budgeted $234k for 900 links in the backend Stephen Goadhouse
Two boards being considered
Alex Madorsky
➡ BCP: 112 RX links @ $18.3k based on KU095 FPGA
➡ APd1: 100 RX links @ $28.1k based on VU160 FPGA (more logic and mezz connection)
Q11 Options without CSC mezzanine: 9-10 boards
➡ BCP → 18.3k×9 = $165k Meets all requirements, decision in 2021
Q12 ➡ APd1 → 28.1k×10 = $281k
Andrew’s idea: design CSC mezzanine with 60 links @ $2.5k
➡ Saves at least $40k, requires R&D and adds complexity
Q13
Remote programming of DCFEB/ALCT easier from FED since there is no need to
load firmware only to specific chambers, and there might ways of doing it anyway
Q14 Want duplex connection with ODMB for PROM-less programming and increasing
118 Mb buffers (KU095) with up to 13×60 = 780 Mb
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 17GEM upgrades
η
Overview of the GEM upgrades
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
θ° 84.3° 78.6° 73.1° 67.7° 62.5° 57.5° 52.8° 48.4° 44.3° 40.4° 36.8° η θ°
8 1.2 33.5°
R (m)
DTs
New ME0 station MB4 New GE2/1 ring
CSCs
RPCs
RB4 1.3 30.5°
7
➡ 6-layer GEM detectors covering 2.0 < |η| < 2.8 ➡ 2-layer GEM detectors GEMs
covering 1.6 < |η| < 2.4
Wheel 0 Wheel 1 Wheel 2 iRPCs
➡ Adds trigger capabilities and offline ➡ Adds redundancy/complementarity
ME0 1.4 27.7° to
acceptance6 for η = 2.4 to 2.8 MB3
ME1/3
GE1/1+ME1/1 and ME2/1 stations
RE1/3
RE2/3
RE3/3
RE4/3
RB3
➡ Installation in 2024-25 ➡ Installation in 2022-23 1.5 25.2°
ME2/2
ME3/2
ME4/2
MB2
5 RB2 1.6 22.8°
MB1
ME0 and GE2/1 follow the installation 1.7 20.7°
RE1/2
RE2/2
RE3/2
RE4/2
4
of GE1/1, which will happen in LS2
RB1 1.8 18.8°
ME1/2
1.9 17.0°
Solenoid magnet 2.0 15.4°
3 2.1 14.0°
ME2/1
ME3/1
ME4/1
2.2 12.6°
RE3/1
RE4/1
GE2/1
2.3 11.5°
HCAL 2.4 10.4°
GE1/1
2
ME1/1
2.5 9.4°
ECAL 2.8 7.0°
ME0 Steel 3.0 5.7°
1 HGCAL
Silicon
tracker
4.0 2.1°
5.0 0.77°
Alexei Safonov
0
0 1 2 3 4 5 6 7 8 9 10 11 12 z (m)
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 19Lessons learned from GE1/1
Gilles de Lentdecker
Chamber
components (GE1/1) Brian Dorney
Experience from GE1/1 crucial for GE2/1
and ME0
GE1/1 Readout Design
Lots of discussion on how to minimize noise
and couples
• RO AGND cross-talk onto
(AC) readout boardnot
GEB layers, andgood
GEB
Side View
& GEB
RO Connector
(OUTER)
GEB + Layers
Anode + RO AGND
FR4 (3.2 mm) ROB
Anode
• Anode strips couple (AC) to GEB layers, not good
– Lines from readout via’s to readout connector are
Manuel Franco Sevilla
unshielded
Summary of CSC/GEM upgrade workshop Slide 20Noise in GE1/1
Brian Dorney
Efficiency:
High
2014 H2 levels of noise
& H4 Test Beamswith v2 electronics had a significant impact on the efficiency
Noise Comparison
• Right: GE1/1 http://cdsweb.cern.ch/record/2162881?ln=en
2014efficiency vs.
measurement
applied drift
at H4 based on VThreshold1 = 15 DAC Units
voltage 2016 measurement
TOTEM VFAT2 at cosmic stand
hybrid and based on v2
• Purplebackend
TURBO curve electronics
shows
performance for
omparison Noise Comparison
Ar/CO2 (70/30)
Dramatic
u
• Efficiency at VDrift
of 3.28 kV ~97%improvement
Results obtained with TOTEM
with v3 electronics
VFAT2 Hybrid and TURBO back-
end electronics
N/A N/A
Cameron Bravo
v2 v3a
B. Dorney 4/10/18
CMS GEM/CSC Forward Muon Upgrade
Workshop
19
N/A u
N/A u u N/A N/A
u
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 21HG
v3 should be OK for GE2/1 - ME0 HG Noise too high
large cap
Marcus Hohlmann
Paul Aspell
Don’t use HG for
Expected S/N ~ 9.5 for MIP is ok
VFTAT3b dynamic range reasonable for ➡ ENC ~ 0.42 fC, MIP charge ~ 4 fC
expected charge ➡ Cross talk ~ 12%, can only reduce with more channels or
Hit rate per channel
Hit rate per channel up to 2 MHz less resolution
➡ Input capacitances measured at Lappeenranta
➡ GE2/1 has < 2.6 kHz, ME0 has < 46 kHz
✴ Ctotal = 2×Cinter-strip + Cground + Chybrid = 2×18.5 + 10 + 4.6 = 52 pF
TP FE setting 000 001 011 111
Measured
Peaking Time
15ns 25ns 35ns 45ns MG
33e/pF (HG 45ns for low cap only) Analog front-end baseline
+ 30e/pF (MG 45ns for high cap) restoration below 500ns
ork in MG for large cap (GE21). Hence completely ready for the
next hit after 500ns
hybrid adds ~4.6pF, hence total ~ 52pF (worse case) Rate capability up to 2MHz per
ENC ~ 2632 e- (0.42 fC)
ould give ENC ~ 2632e (0.42fC) channel
No problem of hit rate for GE21
PV gives S/N = 9.5 or ME0
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 22
ean gives S/N = 26Strip side
Work on the readout board
Ana Ovcharova
Workflow: Overview
Groups at UCSB and BARC working on the layout of GE2/1 modules
Makaranda Dixit
Readout Board 101 Strip side
Connector side
✦ Bottom: radial strips with constant spacing
✦ Top: signals routed to connectors
nsuming ✦ Density:
nges may • GE2/1 boards → 1536 traces
• ME0 board → 3,072 traces
Alternative Readout Design
Workflow
✦ • Use
produce technical drawing of strip sideFR4
(DXF)as a better dielectric to reducing AC
Current specifications: Grounding
coupling between GEB & RO
✦ import in Altium and build up connector side
GE2/1 & ME0 Readout Boards 3
✦ “finishing touch” - screw holes, copper plane,
Agreed to produce following prototype ROBs to study noise
grounding • Make a standard readout
Grounding
Connector
✦
side
2.3 mmX mm
trace under thick then
connector feeds GNDglue
pads via 0.2 mm “whiskers”
• connected to copper plane with 0.5 mm “whiskers”
➡ Size of GE1/1 but GE2/1 strip lengths thicker piece above (X –copper 3.2 mm
islands thick)
retained ✦
Copper GND
Producing layout “by hand” very time consuming clearance between traces & GND plane: 1 mm
✦
“islands”, needed or
➡ No groundorder
fill oftooperations
✦ reducematters
capacitance – Like
on how MicroMegas
noisy edge
→ even small changes may or
strips uRWELL
Q: Can we improveusebased pre-preg
on previous test results? noise contributor?
Related discussion
➡ No groundrequire
fill redoing significant amount of work
and multiple layers with more space between
Side View GEB and RO traces
Cameron’s talk: “noise in edge strips decrease as spacing between trace and
critical to automate as much as possible
✦ ground plane was increased“
ROdifference
Tuure’s talk on M4 prototype tests: “No clear Connectorbetween slots” [with
Top View
1, 2 or 3 mm clearance to ground plane]
GEB + Layers
Possible FR4 (3.2 - X mm) Pins floating
Anode + RO AGND
Ana Ovcharova (UCSB) multilayer ROB GE2/1 & ME0 Readout Boards FR4 (X mm) 3
Anode
1 mm clearance between
Also, GEB with additional pre-preg layer on bottom B. Dorney 4/10/18
CMS GEM/CSC Forward Muon Upgrade
Workshop
37
Connector
traces and GND plane,
optimal?
Too wide/narrow?
grounding, ok?
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop
Ana Ovcharova (UCSB) GE2/1 & ME0 Readout Boards Slide 23
10FlexPCB
Upgrade Workshop (CLL Texas)
CMS CSC/GEM Forward Muon
Michele Bianco
Several FlexPCB prototypes will be prepared and validated for their use
100 mm
Jason Gilmore
in GE2/1 and ME0
214.5 mm
Option A ~ 40 x 50 mm cutout in the GEB
Option A ~ 40 x 50 mm
GE1/1 Hybrids Flexcutout
PCB in the GEB
214.5 mm
HRS 140
GE1/1 Hybrids
GEB to Hybrids connector
Flex PCB HR
SHRS 140
7
GEB HR GEB
140
50 mm
GEB to Hybrids connector
GEB S GEB
140
RO Boards
RO Boards Option C
Panasonic 100 Panasonic 130
Panasonic 100 Panasonic 130
Option B
Option B GE1/1 Hybrids Flex PCB
Option C
Flex PCB HRS 140
GE1/1 Hybrids HRS
GEB to Hybrids connector
GEB 140HRS 140 GEB
GEB to Hybrids connector HRS
GEB 140 GEB
RO Boards
RO Boards
Panasonic 100 Panasonic 130
Panasonic 100 Panasonic 130
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 24GEB
5( Yong Ban
Control bending of GEBs
➡ Pressing procedure, rigid frame for shipping, even out copper if possible
➡
CMS&TripleAGEMs&
Dedicated GEB prototypes to be produced to study maximum length of SLVS signals
Also need to make sure dimensions are ok for manufacturing
GE1/1(TripleHGEM( GE2/1(TripleHGEM( 118##cm#
3072#channels/detector#
442k#channels#in#GE1/1#
184##cm#
50#cm#
pleHGEM( Chimney#
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 25GE2/1 OptoHybrid
Mike Matveev
Option to use 4 OHs Various advantages
➡ 2 Master, 2 Slave ➡ Simpler mechanical design, installation and maintenance
➡ 1 Master, 3 Slave ➡ Simpler GEB design, shorter traces, better signal integrity
➡ Potential savings in FPGA cost
GE21 Readout
Nominal is 2 OHs with GBTX GE21 Optohybrid with “Light”
Option to use 4 OHs
GEB4 - One OH per GEB, serves 12 VFAT3 ASIC
GEB4 - Need 2 GBTx + 1 SCA (or 1 LpGBTX)
OH
- Need to provide 12 VFAT3 x 9 pairs = 10
OH - One 3.2Gbps link (one fiber) to OTMB
GEB3
GEB3 - One 3.2Gbps link (one fiber) to uTCA pr
VTRX OH - Need 2 VTRx (GBTx) and 1 VTTx (trigge
VTTX
VTRX - Few S6/V6/A7/K7 candidates, the cheap
VTTX GEB2
GEB2 VTRX
OH Advantages
OH - Simpler mechanical design, installation
GEB1 - Simpler PCB design, shorter traces, bet
GEB1 OH - Potential saving in FPGA cost
● Manuel
Functionally
Franco Sevilla
similar to OHv3 for GE11. Serves 24 VFAT3 (two ● GEB
System boards).
Overview
Summary of CSC/GEM upgrade workshop Slide 26
- Same proven Xilinx XC6VLX130T-1FFG1156C FPGAME0 OptoHybrid
Andrew Peck
Option to do FPGA-less OH
➡ FPGA-less Optohybrid
Eliminates FPGA risks
Option to solder optics and lpGBT directly onto GEB
➡ Reduces footprint → easier GEB/RO routing
➡ No high speed signal crossing entire GEB
➡ Increases fibers from 18 to 48
CERN VL+ Optics
LpGBT tx
trig 320 Mbps x24
10.24 Gbps
clock 40 MHz x3
2.56 Gbps
LpGBT GEB Connectors
tx/rx 320 Mbps x3
LpGBT rx
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 27Backend
Evaldas Juska
Biggest concern for GE2/1 is links, for ME0 is logic
➡ Various possibilities based on BCP/ADp1 depending on ME0 logic actual needs Stephen Goadhouse
9. ME0 and GE2/1 links
Common GE2/1-ME0 backend system would be optimalversion 2 Evaldas Juska (TAMU)
Alex Madorsky
ME0 and GE2/1 as a common system, with more links than CTP7
Trigger links
ME0 GE2/1
20 degree chamber layer LpGBT links
20 degree chamber layer
Total: 216 layers Total: 72 layers (2 per chamber)
DAQ/TTC links
(6 layers per chamber)
OH 2
ME0 layer
CSC OTMB
OH ATCA backend card
Requires 90 RX + 41TX
100Gb/s DTH interface
3 chambers (18 layers) Hard to split to 2 smaller FPGAs
(e.g. VU9P should work) OH 1
per ATCA card
100Gbs 11x9.6Gbs
DAQ
DTH & EMTF 6 layers per ATCA card
TTC
Note: if GE2/1 will use GBTX,
there will be 4 more TX and RX
12 backend cards in total per layer.
(24 more per ATCA card needed)
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 28Trigger
Current OTMB Pattern Finding Logic:
Improvement of CLCT resolution in CSCs
Pattern Unit
x224
Best 1 of 32
Sorters
x7
delay flip-flop
Best 1 of 7
Sorter
x1
1st CLCT
Look-up table can be implemented in OTMB to “fit”
Busy
Logic patterns
Best 1 of 7
Busy Sorter
2nd CLCT
Best 1 of 32
Busy Sorters
delay flip-flop
Andrew Peck
➡ Sufficient resources in OTMB FPGA, not clear in TMB x7 x1
Will Nash
Modified
➡ No increased latency, LUT inOTMB Pattern
place of Finding Logic:
flip-flop
Best 1 of 32 Best 1 of 7
Pattern Unit
Sorters
Lookup Tables
Sorter 1st CLCT
x224 x7 x n_pats * 7 * 2 x1
Busy Best 1 of 32 Best 1 of 7
Logic Busy Sorters Lookup Tables
Busy Sorter 2nd CLCT
Comparator Code Lookup Position Resolution Comparator Code Lookup Slope Resolution
x7 (shared with 1st lookup) x1
RMS drops from 0.177 ! 0.089 10 !
RMS drops from 0.115 0.076
Improvement on position and slope resolutions 8
EMU Phase II Workshop April 2018
Consistent with PLCT resolution (0.173 ! 0.081) Consistent with PLCT resolution (0.112 ! 0.073)
Can we use it in EMTF?
3 3
➡ 300
×10 ×10
Current Patterns Current Patterns
Entries 5525155
Position Slope
250 Entries 5525155
Q15 250
Mean
Std Dev
−0.0002432
0.1773
Mean
Std Dev
8.593e−06
0.115
Segments / 0.01 [strips/layer]
resolution resolution
Underflow 1179 Underflow 133
Segments / 0.01 [strips]
Overflow 1932 Overflow 96
Comparator Code 200 Comparator Code
200
Entries 5525155 Entries 5525155
Mean −5.192e−05 Mean −5.661e−07
Std Dev 0.08931 Std Dev 0.07647
Underflow 947 150 Underflow 40
150
Overflow 1082 Overflow 44
100 100
50 50
0 0
−1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1
Position Difference [strips] Slope [strips/layer]
W. Nash (UCLA) Improving CLCT Resolution April 10th, 2018 14 / 20 W. Nash (UCLA) Improving CLCT Resolution April 10th, 2018 16 / 20
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 30cal trigger
Trigger implementation
Sven Dildick
s
L1Mu-trigger with GEM/ME0
Including GEMS in local CSC can have several advantages
➡ Reduced input rate to L1Mu, efficiency recovery at high PU
• Usage of the bending angle information at the L1Mu-trigger
➡ Removal of ghosts allows
for a large rate reduction (even in the difficult high-eta
➡ Bending region)
angle measurement, correct stub timing
• Additional hits in GEM and ME0 chambers improve the efficiency
e
even at ultimate pileup 200 foreseen EMT++
at Phase-2includes
CMS new RPC and GEM detectors Jia Fu Low
t ➡ Higher efficiency and better pT assignment
pTresol
uti
on
➡ Studying NN for further pT improvement
EMTF EMTF++
3
Possible to send OTMB data
directly to EMTF?
➡ Bypassing MPC Q7
Incorrect Less spread at
charge assignment high pT
5Summary
Significant progress addressing remaining CSC open questions
CSC questions for LS2 CSC questions for LS3
1. Powering down GBTx in xDCFEB/ALCT? 8. Which FPGA for the ODMB?
In design, to be tested Artix-7 + lpGBT meets all requirements, decision in 2019
2. Duplex connection on the xDCFEB’s VTRx? 9. Which optical transmitter for the ODMB?
Not needed Firefly and VL+
3. Replace Finisars in DCFEBs with VTTx on adaptor board? 10. Reuse ODMBv1 in ME34/1?
Produce prototype of Option 2 11. Program DCFEBs/ALCTs from ODMB instead of FED?
4. OTMB copper inputs needed? From FED
Not needed 12. Which ATCA board for FED?
5. How many spare fibers? BCP meets all requirements and good price, decision in 2021
None needed 13. How to partition DAQ system?
6. GE2/1 → OTMB connection? 9 BCPs, 6 BCPs with CSC mezzanine
Get quote for Firefly split into 2 MTP12s 14. Do we want/need 2-way ODMB/FED communication?
7. Increase OTMB bandwidth with direct connection to EMTF? Yes, for PROM-less programming and increased buffering
15. Can improved LCT resolution improve triggering?
Defined next steps towards full GE2/1 and ME0 designs
Manuel Franco Sevilla Summary of CSC/GEM upgrade workshop Slide 32Backup
ODMB DAQ rates extrapolation to HL-LHC
LCT*L1A Rates 2016 Data
Rate/lumi seems constant a high luminosity
Baseline is Stan’s quadratic extrapolation
First look at
→ quadratic extrapolation Upgraded ME1/1 Rates
➡ Linear with L1 rate × linear with luminosity
ME2/1 L1A*LCT Rate/Luminosity vs Luminosity LCT*L1A Rates 2016
Reality is probably between linear and quadratic
ME1/1
LCT*L1A Rate/Luminosity (Hz/10 30cm -2s-1)
2015 ME2/1
0.6
2016 RLCT⇥L1A ⇡ Rµtrig + CµPU ⇥ L + Crandom ⇥ L ME3/1
Rate/Luminosity (Hz/ (10 30cm -2s-1)
0.5 ME4/1
0.5
0.4
➡ Rµtrig: rate of triggered muons
➡ CµPU: additional muons coming from PU
0.4
0.3
➡ Crandom: random hits
0.3
0.2
When lumi low, Rate/lumi high because trigger tables turn
Rµtrig would be constant with luminosity if the fraction
on non-restrictive paths. of the L1 rate dedicated to muons was constant
0.2
0.1 Asymptote should describe HL-LHC conditions at full lumi
CµPU is linear with lumi, but probably small
0.1
0Key is size of Rµtrig vs Crandom×L
0
0 2,000 4,000 6,000 8,000 1e+04 1.2e+04 1.4e+04
Luminosity (10 30cm-2s-1) If the
➡2,000 former
4,000 is large,
6,000 you’d expect 1e+04
8,000 rate/lumi1.2e+04
to keep1.4e+04
decreasing →
Luminosity (10 cm s )
30 -2 -1
current data rates would be overestimated
As expected rates have leveled off
Manuel Franco Sevilla (O)DMB upgrade Slide 34ODMB Two board designs: ODMB7 - ODMB5
72 ODMB7 for ME1/1 108 ODMB5 for ME234/1
CSC 7 DCFEBs + PPIB (already installed)
CSC 5 DCFEBs →
ME1/1 Only 2 copper connectors needed ME234/1 5 copper connectors fit in front panel
LVMB LVMB
C op Cop
per per
DCFEB2 DCFEB4
DCFEB2 DCFEB4 DCFEB6
50 22
DCFEB1 DCFEB3 DCFEB5 DCFEB7
VME
DCFEB1 DCFEB3 DCFEB5
VME
ODMB5
Fibers 12
ODMB7
5 50
50 50 50 50 50 50 50
Fibers 12
CCB
7
50
CCB
50
50
PPIB (Patch panel) Copper 50 Copper
50
ME1/1 TMB
50 ME234/1 TMB
DDU (@ 20+ Gbps) DDU (@ 10+ Gbps)
Two very similar designs with ME1/1 ME234/1 Outer rings
main difference in front panel Pre-LS1 DMB DMB DMB
LS1-LS3 ODMB DMB DMB
Notation Post-LS3 ODMB7 ODMB5 DMB
Manuel Franco Sevilla (O)DMB upgrade Slide 35Front Panel Real Estate
ODMB Key design changes
ODMB ODMB2015? DMB
ODMB7 ODMB 5
New ODMB7/5 •largely based
LEDs, JTAG, on LS1
Push Buttons, ODMB
not critical on FP
HD50 26pin HD-22
• ME2,3,4/1 LVMB
➡ Similar PCB, with very differentneeds
front 5panels
HD50s and 1 HD-22 LVMB
HD50
HD50
LVMB • ME1/1 needs 3 HD50s LEDs
LEDs
• All need 12 fiber receiver
JTAG New FPGA with• higher speed links (next slide)
All need optical transmitter to FED crate
3 push buttons ➡ Or just to reduce cost if using lpGBT
CFEBs (TTC and Data)
CFEBs (TTC and Data)
20 LEDs
• DMB FP minus LEDs plus free space has room for
HD50
10 Gbps transmitter to receiver.
SNAP12 FED (4 TX, 1 RX)
➡ VL+ (new VTTx) if•compatible
This Scheme works
with for ME2,3,4/1 (CFEB or DCFEB)
schedule
HD50
HD50
DCFEBs (TTC) cases
HD50
• For ME1/1 case, 3 HD50 connectors need to be
DCFEBs (data) 12 RX Firefly to replacerepurposed
Reflex photonics Snap-12
Stabilizer • In principle, could have one set of assembly
HD50
options for ME1/1 connector assignments and a
HD50
DCFEBs (TTC)
HD50
separate set of options for ME2,3,4/1
ODMB7 in ME1/1 ODMB5 in ME234/1
• Not ideal, not good for signal integrity, some
HD50
DDU/PC
(data)
•Front panel similar to the ODMB’s assignments
•Frontare
panel similar
power to the DMB’s
for PPIB
DDU
12 LEDs • Need to maintain separate inventory
•Ability to relay FW to ALCT/DCFEB DDU
(data)
for remote programming Free Space!
Separate
D.Wood, MEx/1 off-chamber electronics
PCB designs for ME1/1 and ME2,3,4/1 may be necessary 8Slide 36
Manuel Franco Sevilla (O)DMB upgradeODMB Remote programming of ALCT/DCFEB
xDCFEB
ODMB7
VTTx
FED VTRx GBTx
8 Finisar
DDR3
RAM
Zynq FPGA TX RX VSC3308
FTLD10CE3C
ALCT-LX100
SD card VTRx GBTx
Additional requirement for ODMB7 is remote programming of ALCT/DCFEBs
FED would send FW to the ODMB7, which would fan it out to the ALCT/DCFEBs
➡ Needs to avoid FPGA in ODMB → use VSC3308 repeater or similar
Manuel Franco Sevilla (O)DMB upgrade Slide 37ODMB Option: FW from ODMB7
ODMB7 VTTx xDCFEB
VTRx GBTx
Finisar
FPGA
FTLD10CE3C ALCT-LX100
VTRx GBTx
Pros
➡ Allows to upload different firmware to individual chambers
➡ A bit cheaper
Cons
➡ Longer boot-up time (perhaps still in the shadow of other boards)
Manuel Franco Sevilla (O)DMB upgrade Slide 38ODMB Schedule
Early schedule driven by engineering resource optimization
Title 2014 2015 2016 2017 2018 2019 2020 2021 2022 2023 2024 2025 2026
2014 Preparation
2015 2016 2017 2018 Prototypes
2019 2020 2021 2022 Float
2023 2024 Installation
2025 2026
CSC review of electronics design completed (HM) Jun 1, 2016 Jun 1, 2016 Design Production
ODMB optical transmitter and FPGA tests Jan 1, 2019 Jul 1, 2019
ODMB optical transmitter and FPGA chosen (HM)
FPGA chosen Jul 1, 2019 Jul 1, 2019
(key milestone)
ODMB prototype design Jul 2, 2019 Aug 26, 2019
ODMB prototype testing Oct 8, 2019 Dec 16, 2019 PRR
ODMB PRR Apr 7, 2020 Apr 20, 2020
ODMB ready for production (HM) Jul 6, 2020 Jul 6, 2020
ODMB pre-series produced Jul 7, 2020 Aug 17, 2020
ODMB Production and testing Oct 13, 2020 Jun 21, 2021
ODMB integration Jun 23, 2021 Dec 7, 2021
ODMB production firmware development Mar 2, 2020 Feb 12, 2021
ODMB ready for installation (LM) Dec 7, 2021 Dec 7, 2021
CSC Readout electronics EDR (EM) Today Feb 1, 2023 Feb 1, 2023
CSC Readout electronics ready to install (HM) May 2, 2025 May 2, 2025
Manuel Franco Sevilla (O)DMB upgrade Slide 39You can also read
