CS250 VLSI Systems Design - Fall 2020 John Wawrzynek with Arya Reais-Parsi (virtual GSI) - Berkeley
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CS250
VLSI Systems Design
Fall 2020
John Wawrzynek
with
Arya Reais-Parsi (virtual GSI)
Lecture 01, Introduction 1 CS250, UC Berkeley Spring 2017
First Thing …
‣ This class has always been and will continue to be highly interactive :
not recorded.
‣ It is like a “studio-based art class”. Students show and discuss their art
and get feedback and ideas from other students and the instructor.
Minimal emphasis on lectures.
‣ We found this to be a very effective for students to advance their
design skills. But it’s success depends on commitment by everyone.
Everyone is expected to stay engaged and offer comments and
questions.
‣ Challenging now in the days of the pandemic.
‣ It can work over zoom, but it takes more effort by all of to stay
engaged. In my experience with teleconferencing and (many) zoom
meetings over these months, teleconferencing works best with video
enabled.
‣ If your situation prohibits you from comfortably keeping your video on,
please let me know. Other wise I’ll expect that you keep it on.
‣ Stay muted, but un-mute and interrupt at any time!
Lecture 01, Introduction 1 2 CS250, UC Berkeley FA20
John Wawrzynek (pronounced “Warsnik”)
Professor in EECS
‣ Berkeley faculty since 1989
Teaching:
‣ CS61c, EECS151/251A, other hardware and architecture
courses
Research:
‣ Computer Architecture, Reconfigurable Computing, Digital
Design Methodologies,
‣ Advanced Wireless Systems
Administrative:
‣ CS Vice-chair for Graduate
Matters
3
‣Chair Berkeley Campus Conflict
of Interest Committee
Degrees:
‣ MSEE UIUC, PhD Caltech
Start-ups:
Former-life: professional musician (bass), Buffalo NY
Lecture 01, Introduction 1 3 CS250, UC Berkeley FA20
The context for CS250
‣ Number 1 reason for students to enroll in CS250:
‣ “Gain more experience in digital design - specifically
targeting custom ICs”
‣ Components of Digital Design:
1. Logic and Transistor Circuits and low-level blocks:
‣ how to achieve desired function of low-level chip building
blocks
‣ state transitions and clocking
‣ performance/cost/power tradeoffs
‣ physical realization concerns (floorplanning, clock
distribution, pwr distribution)
‣ Provides “Bottom-up” knowledge
Lecture 01, Introduction 1 4 CS250, UC Berkeley FA20
The context for CS250
‣ Components of Digital Design:
2. Chip Architectures and high-level blocks:
‣ How building blocks are assembled to achieve high-level
functionality
‣ Processor Cores (CPUs), chip-multiprocessors (CMP), Field
Programmable Gate Arrays (FPGAs), Coarse-grain
Reconfigurable Arrays (CGRAs), Domain processors (GPU, DNN
engines, DSPs), algorithm specific accelerators (graph processor,
video codec, encryption engine)
‣ The programmable architectures start from a standard
“execution model” - ISA. Accelerators start from an algorithm
or set of algorithms.
‣ We learn their structure and degrees of freedom in
functionality and implementation tradeoffs
‣ Provides “Top-down” knowledge
Lecture 01, Introduction 1 5 CS250, UC Berkeley FA20
The context for CS250
‣ Components of Digital Design:
3. Design Representations/Methodologies/Tools
‣ Representations give us a way to abstract, enter, manipulate,
analyze, our design leading to an implementation.
‣ Ex: data-flow graphs, Bool Equations, Verilog, logic gate netlists, GDS
‣ Methodology - roadmap that we follow to implement our designs
‣ The tools analyze and automate aspects of implementaion and
optimization (convert from one from to another)
Lecture 01, Introduction 1 6 CS250, UC Berkeley FA20You’ve learned the basics already
‣ What we assume you know at this point:
1. Circuits: Basic logic design and optimization, CMOS
implementations of logic functions and state elements.
Structure of basic building blocks: arithmetic, FSMs,
memory blocks, edge-triggered synchronous clocking.
2. Architecture: Basic RISC CPU structure, FPGA fabric
structure, and in principle - how to design an accelerator
3. Tools: some design flow for ASIC or FPGA - from Verilog/VHDL
to mapping to chip or fabric. Most likely with industry
standard tools from Cadence, Synopsys, and Mentor
Graphics.
‣ We assume that you understand how to map function to
circuits, but not much experience with optimization.
Lecture 01, Introduction 1 7 CS250, UC Berkeley FA20Berkeley Digital Design Classes
‣ CS152/252:
‣ CPU structure, CMPs, memory systems, on-chip interconnect (NoCs)
‣ EECS151/251A:
‣ Focus on RISC-V microarchitecture, Xilinx FPGA fabric architecture.
Synchronous logic design. Arithmetic blocks. ASIC + FPGA design
flows.
‣ EE241B:
‣ Extensive CMOS transistor level circuit analysis and optimization for
performance/cost/power.
‣ EE250:
‣ More practice with design tools. Synopsys with “academic” process
design kit (PDK)
‣ Alternative design methodology - Chisel based (not Verilog/VHDL)
‣ Emphasis on design optimization - Design Space Exploration (DSE)
Lecture 01, Introduction 1 8 CS250, UC Berkeley FA20Design Optimization
‣ Industrial View:
‣ Meeting some set of prescribed (or desired) constraints on
power, cost, and performance.
‣ How do we define these?
‣ Academic View:
‣ Mapping the Pareto Optimal Frontier
“Pareto Optimal” Frontier
Performance
(tasks/sec)
high-performance at high-cost
Cost (# of components)
low-performance at low-cost
‣ How do we find these points?
Lecture 01, Introduction 1 9 CS250, UC Berkeley FA20Design Space Exploration
‣ CS250 has traditionally focussed on:
‣ methodology for DSE
‣ practice on some particular function (accelerator, processor,
…)
‣ Processor cores, Memory controllers, image processors, cordic
blocks, audio processor, radio/communications blocks
‣ Mapping the Pareto frontier has been the goal
‣ What are the tradeoffs to be made?
‣ Pipelining, Serialization versus parallelization gives us a way
to trade area for performance, and area for power.
‣ Designs are specified as “parameterized generators” allowing
parameter sweeps to build and analyze a variety of designs.
‣ Chisel helps in building generators.
Lecture 01, Introduction 1 10 CS250, UC Berkeley FA20Chisel: Constructing Hardware In a Scala Embedded Language
❑ Embeds hardware-description language in Scala,
using Scala’s extension facilities: Hardware
module is just data structure in Scala
❑ Different output routines generate different types of
output (C, FPGA-Verilog, ASIC-Verilog) from same
hardware representation
❑ Full power of Scala for writing hardware
Chisel Program
generators
▪ Object-Oriented: Factory objects, traits, overloading, etc.
Scala/JVM
▪ Functional: Higher-order functions, anonymous
functions, currying C++
code FPGA ASIC
▪ Compiles to JVM: Good performance, Java Verilog Verilog
interoperability
C++ Compiler
FPGA Tools
Software ASIC Tools
Simulator FPGA
Emulation
GDS Layout
11
EE141ASIC tools, PDKs, Fabrication
‣ Chip design relies heavily on CAD tools:
‣ Logic synthesis/mapping, layout, functional/timing/power
analysis, verification
‣ And on “process design kits” (PDK)
‣ geometric design rules, process electrical paramaters, cell
layouts, cell models for simulation and analysis, …
‣ A problem for us: From Tim Ansell, Google
‣ commercial tools are very complex to use (some efforts recently
here with “Hammer” make it somewhat easier, though).
‣ Not well documented (companies that design chips have teams
of full-time staff to maintain tools).
‣ Support has been poor - companies focus on paying customers.
‣ PDKs for real IC processes are available only under NDA.
“Instructional” PDKs have been used instead, designs can't be
fabricated
‣ Open source design tools and PDK?
Lecture 01, Introduction 1 12 CS250, UC Berkeley FA20New: Open Source ASIC tools,
PDKs, Shuttle runs
‣ Tim Ansell - Google
OpenLANE is an automated RTL to GDSII flow based on
several components including OpenROAD, Yosys, Magic,
Netgen, Fault and custom methodology scripts for design
exploration and optimization. The flow performs full ASIC
implementation steps from RTL all the way down to GDSII -
completed SoC design examples have fabricated.
From Tim Ansell, Google
Lecture 01, Introduction 1 13 CS250, UC Berkeley FA20Open PDK
‣ Skywater Technology - 130nm Fabrication
From Tim Ansell, Google
Lecture 01, Introduction 1 14 CS250, UC Berkeley FA20Google Sponsored Shuttle Runs
‣ Wouldn’t it be good to actually fabricate what you designed?
From Tim Ansell, Google
Lecture 01, Introduction 1 15 CS250, UC Berkeley FA20Connecting CS250 Project to
Research
‣ Traditionally this course (and perhaps others) tries to make
a connection to ongoing research projects.
Lecture 01, Introduction 1 16 CS250, UC Berkeley FA20Berkeley Open Reconfigurable Architecture (BORCA)
■ Design a "better" architecture and make it
publicly available as a starting point for new
research and development (academia and
industry).
■ RISC architectures a good example (RISC-V).
■ A rethinking of reconfigurable architectures
through a detailed evaluation of:
■ current architectures,
■ scholarly work,
■ application targets, and
■ design methodology trends.Problems with Existing Reconfigurable
Architectures
■ Primarily designed as standalone chips need a IP
"block" for SOCs.
■ Current tool chains are too slow need new
interconnect architectures, better tools
■ State of the art arrays probably not be power/area
efficient re-architect the arrays and use novel circuits
■ Existing arrays have proprietary architectures and tools,
stifling innovation open architectures and tools
■ Commercial arrays don’t support dynamic
reconfiguration well.Approach
Architecture innovation must go hand in hand with tool development.
Architecture innovation must go hand in hand with chip realizations.
1) Build on and improve open source mapping tools.
2) Develop agility in ASIC block design from the start.
3) Understand current state-of-art array designs.
4) Review past studies on architecture variations and on tools.
5) Assemble set of benchmarks.
6) Focus on interconnect.
7) Build "generator" for area/power efficient reconfigurable array.
Propose architecture Develop Physical model
Evaluate efficiency on benchmarks
Should lead to an understanding of cost benefit tradeoffs (map out the Pareto
optimal frontier).Proposals for this semester:
‣ Use the open-source design tools: openLane
risky - tools might break (but we have the source!)
‣ Use with open-source PDK: Sky130-PDK
‣ Focus design project on open reconfigurable architecture
‣ Target shuttle run for fabrication
Can we make a November tapeout deadline?
Lecture 01, Introduction 1 20 CS250, UC Berkeley FA20Mandatory Sur vey
1.Describe your experience(s) with previous courses in digital design.
For instance, did you take EECS151/251A at UCB and which lab did you
take? If not at UCB, where and which digital design courses did you
take. Give project details.
2.Outside of your course experience described above, have you had any
additional experience doing digital design and using ASIC and/or FPGA
tools?
3.Have you ever studied design tools from the point of view of the
algorithms that they use? If so, describe your experience.
4.What do you expect to get out of this course? What is your main
objective in taking it?
5.We are proposing to focus this semester on the design of
reconfigurable arrays (FPGAs and perhaps coarse grain arrays).
What do you think about that proposal?
6.Do you anticipate a timezone mismatch or any other issue that would
prevent you from participating live in the class meetings over zoom?
Lecture 01, Introduction 1 21 CS250, UC Berkeley SP16End of Introduction
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