Closed-Form Analytical Equations to Transient Analysis of Bang-Bang Phase-Locked Loops
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Closed-Form Analytical Equations to Transient Analysis of
Bang-Bang Phase-Locked Loops
F. Mohseni Kolagar* and H. Miar Naimi**
Abstract: In this paper an exact transient analysis of Bang-Bang PLLs (BBPLLs), as a
nonlinear system, is presented. New equations are proposed for expression of transient
behavior of the BBPLL with first order filter in response to phase step input. This approach
gives new insights into the transient behavior of BBPLLs. Approximating transient
response to reasonable specific waveform; the loop transient time characteristics such as
locking time, peak time, rise time and over shoot are derived with acceptable accuracy. The
validity of the resulted equations is verified through simulations using MATLAB
SIMULINK. Simulation results show the high accuracy of the proposed method to model
BBPLLs behavior.
Keywords: Bang-Bang PLL, Nonlinear Operation, Transient Analysis, CDR Circuits.
1 Introduction1 nonlinear behavior of the BBPLL, these inputs cause
The use of bang-bang phase locked loops has become responses with two different general forms depending
increasingly common in a lot of communication on the input step size. Some simple equations have been
systems, especially in clock and data recovery (CDR) presented to express the locking time of the BBPLL in
systems [1]-[4]. Also these types of PLLs are widely [11] and [12]. These equations are limited only for
used at the higher speed process. These systems use a particular conditions which is called cycle slipping.
bang-bang phase detector (BBPD) in the loop, which These researches are focused on the frequency step
samples data as a part of the phase detection process, response. Also there exists no expression for other
therefore there exists no systematic phase error between features of transient time; rise time, peak time, settling
the data signals and the recovered clock signals. BBPD time and over shoots.
quantizes the phase error between input (data) and This paper presents a novel method to derive the
output (clock) with 1-bit resolution. For this reason, closed form equations to clarify the transient behavior
these types of the PLLs suffer hard nonlinearity. This of the BBPLLs. In this method a parameterized
behavior of the BBPLLs causes that the researchers waveform of the output excess phase is estimated and
make an effort to analyze it. BBPLL circuits must equations for unknown parameters are derived using
satisfy some specifications such as speed, stability, differential equations governing on the BBPLL.
capture range and phase noise, posing challenges to The rest of the paper is as follows: Section 2
system designers. Most researches focused on jitter introduces BBPLL model with first order filter and a
analysis (see [5]-[10]) but there exists a few researches brief review of the existing methods. Section 3
on the transient analysis. Design of the BBPLL in describes the proposed methodology to derive the
higher speeds is the most important reason to analyze equations for locking time, peak time, rise time and over
the BBPLL in time domain. Transient behavior of a shoot. A new technique based on an estimated model for
BBPLL in response to the phase and frequency step output is presented to derive equations for transient
inputs is a main issue in time domain that this paper has response in this section. Simulation results will show
focused on phase step response. Because of the validity of this method in section 4. Finally, section 5
gives conclusions.
Iranian Journal of Electrical & Electronic Engineering, 2011. 2 BBPLL with First Order Filter
Paper first received 8 Nov. 2010 and in revised form 10 July 2011. Consider two cases of the BBPLL; BBPLL with
* The Author is with the Integrated Circuits Research Laboratory,
Electrical and Computer Engineering Department, Babol University of
zero order filter and BBPLL with first order filter.
Technology, Mazandaran, Babol 47148-71167, Iran. References [2] and [5] have illustrated the operation of
E-mail: f.mohseni.el@gmail.com. these two cases clearly. Due to the low speed and small
** The Author is with the Babol University of Technology, capture range of the BBPLLs with zero order filter, their
Mazandaran, Babol 47148-71167, Iran.
E-mail: h_miare@nit.ac.ir.
Iranian Journal of Electrical & Electronic Engineering, Vol. 7, No. 3, Sep. 2011 161VDD of the phase difference between the input (data) and the
output (clock). The parameters ϕin (t) and ϕout (t) refer to
Ip phase of input signal and the output signal of VCO,
respectively. vpd (t) is + 1 when the phase difference is
ϕin (t ) vcot (t )
BPD positive and − 1 when phase difference is negative.
VCO
Rp
v pd (t) is shown as (2).
ϕout (t ) v pd (t) = sign(ϕin (t) − ϕ out (t)) (2)
Cp Ip
Ip when v pd (t) is + 1 , I p charges the loop filter and when
is − 1 , discharges the loop filter. This model is the same
BBPLL discussed in [4] and [5]. To introduce BBPLL,
Fig. 1 BBPLL architecture with first order filter at the first we express the basic equations governing on
the BBPLL. Note that the VCO used in Figure 1 is
use is very limit [2]. In contrary, the BBPLL with first assumed linear. So we can write equation (3) for VCO.
order filter is noticeable. Figure 1 shows a BBPLL with
first order filter. This structure adds an integral path to ωout (t) = ωc + k vco vcot (t) (3)
the loop filter of the system. This integral path provides where ωout (t) , ωc and vcot (t) refer to the output
bigger capture range and makes the loop faster. Because
of these compelling advantages, the bang-bang loop frequency, VCO central frequency and control voltage
with first order filter has become a common design of VCO, respectively.
choice for state-of-the CDR designs. For this reason, in In the BBPLL based CDR, with the input data signal
this paper, we have focused on the BBPLL with first shown in Figure 2, in the steady state or locked
order loop filter used as a CDR. condition the output phase (frequency) is twice of the
As mentioned above, the purpose of this paper is to input phase (frequency) [1]. So when the input phase
derive the all information of the transient time. At first, (frequency) changes from its steady state condition, the
the previous works are briefly discussed. Only reference PLL experiences a transient time and the output phase
[2] has indicated phase step response of the BBPLL by (frequency) reaches to a new steady state; twice of the
phase trajectory with discrete time difference equations input new phase (frequency). So in locked condition, the
for BBPLL with first order filter as (1). output phase (frequency) is twice of the input (data). So
in locked condition at the VCO central frequency ωc
θ(t) n2 (nominal condition), we consider the input frequency
= Δ − (n − ) (1)
θbb ξ equal to ωc / 2 in equations governing on the BBPLL.
In above equation θ(t ) refers to excess phase Figure 2 shows the input data and cock data with a
difference, θbb indicates loop phase step that equals to phase error. It is seen from Figure 2 that the frequency
of clock is twice of input data frequency. Using the
2πI p R p K vco t update and n = t⁄t update and t update = 1/ f c . f c is the
relation between phase and frequency as ϕ(t) = ∫ ω(t)dt
central frequency of VCO. A stability factor, ξ is
and introducing the phase step as Δϕin , we can write the
defined in (1) which equals to 2R p C p ⁄t update and a
set of following equations for BBPLL. Input phase and
normalized transient phase step as Δ = θstep ⁄θbb . In output phase are defined as (4) and (5).
equation (1), the time required to reach steady state, ω
ϕin (t) = ∫ ωin (t)dt + Δϕin u(t) = c t + Δϕin u(t)
given a step of Δ is always less than or equal to Δ time 2 (4)
steps, independent of ξ [2]. The resulted phase ϕout (t) = ∫ ωout (t)dt = ωc t + 2πk vco ∫ vcot (t)dt
trajectories show changes of oscillatory transient for the (5)
different values of ξ . These trajectories don't express Since at the nominal steady state, the phase error,
ϕin (t ) − ϕout (t ) , is zero, we express the dynamical
the details of transient behavior of the BBPLL, because
there are no equations to indicate features of transient
time. Therefore it is critical to analysis the BBPLL in
time domain and extract all important times.
Consider a BBPLL with first order filter shown in
Figure 1. The BBPLL consist of a BBPD, charge pump
with current Ip, a loop filter with resistance Rp and
capacitor CP connected series, and voltage controlled
oscillator (VCO) with gain KVCO. The output voltage of
bang-bang phase detector vpd (t) provides a binary form
of voltage as sign(ϕin (t) − ϕout (t)) where it has indication Fig. 2 Input (data) signal and output (clock) signal
162 Iranian Journal of Electrical & Electronic Engineering, Vol. 7, No. 3, Sep. 2011equations of the BBPLL in term of the excess phases. functions such as tanh(αϕe (t)) and arc tan(αϕe (t)) are
So Δϕinu (t ) is the input excess phase denoted by ϕin ,ex (t ) selected, because these functions are more similar to
and K vco ∫v cot (t )dt is the output excess phase, denoted sign function. See Figure 3, when α is increased
tanh(αϕex (t)) converges to sign function. α is an input
by ϕ out ,ex (t ) . So excess phase error is written as (6).
parameter. By changing α, we can make an acceptable
approximation for sign function. We solve equation (9)
ϕe (t) = ϕin,ex (t) − ϕout,ex (t)
by replacing sign function with tanh(αϕex (t)).
(6)
= Δϕin − 2πk vco ∫ v cot (t)dt Substituting (8) into v pd (t) and v pd (t) into (9) and
After locking, as mentioned above, the output phase finally differentiating both sides of (9), results in
is twice of the input, so according to (4) and (5), we differential equation of v cot (t) as follows:
have (7). dv cot (t)
=
ω dt
ωc t + 2 πk vco ∫ v cot (t)dt = 2( c t + Δϕ in u(t)) (7)
2 α.I p .R p (1 − tanh 2 (α.(2Δϕin − 2πK vco ∫ v cot (t).dt)))μ X
As we know, in the locked condition, the output
Ip
frequency is twice of the input. Using this point along ×( −2 πK vco .v cot (t)) + tanh(α.(2Δϕin − 2πK vco ∫ v cot (t).dt))
with equation (7), (6) should be rewritten as (8). Cp
ϕe (t) = 2Δϕin − 2πk vco ∫ v cot (t)dt (8) (10)
To solve (10), consider the set of following
Or we can consider a factor of 1/2 for output excess
equations in state form:
phase ( K vco ∫v cot (t )dt ) instead of factor of 2 for input
x1 (t) = 2πK vco ∫ v cot (t)dt
excess phase ( Δϕin u(t) ) in equation (8). Equation (8)
x 2 (t) = v cot (t) (11)
guaranties that ϕe (t) = 0 is equal to the locked
dx1 (t)
condition. This also can be investigated and verified = 2πK vco x 2 (t)
using simple simulations. dt
Substituting the above equations into (10), result in a
3 Proposed Method differential equation as
3.1 General Procedure of the Proposed Method dx2 (t) dx (t)
= −α.Ip .Rp (1− tanh2 (α.(2Δϕin − x1 (t)))).( 1 )
The method proposed in this paper is based on the dt dt
exact differential equations governing on the BBPLL. Ip (12)
These equations are simply obtained using circuit + tanh(α.(2Δϕin − x1 (t)))
Cp
analysis methods and the equations (1) to (8). At the
beginning, we obtain v cot (t) by analyzing Figure 1 as x2(t) refers to the control voltage of oscillator and x1(t)
indicates the output excess phase. To evaluate the effect
(9).
of approximation of tanh(αϕex (t)) on the behavior of the
I p sign(ϕe (t))
v cot (t) = R p I p sign(ϕe (t)) + ∫ dt (9) system, we numerically solved the equation (12) in
Cp
In equation (9), the term sign(ϕe (t)) is the role of
phase detector output on the filter charging current that
is in the form of ± R p I p ± (I p / Cp )t . tanh(αϕe (t ))
To derive the differential equation of v cot (t) , we
need to define vpd (t).
Increase of α
As mentioned before, the output voltage of BBPD
( vpd (t) ) is as a sign function, this function imposes a
hard nonlinearity on the loop. To overcome this
problem, we introduce a proper function instead of sign.
Because of discontinuity of sign at zero, we suggest
replacing sign with another function which is
continuous and also is very similar to sign function. So
it is possible to apply integral and derivative operators Fig. 3 tanh(αϕ e (t)) function compared with sign.
on it. Among different alternatives, trigonometric
Mohseni Kolagar & Miar Naimi: Closed-Form Analytical Equations to Transient Analysis … 1632.5 2.5
Output excess phase (radian)
Excess phase error (radian)
2 2
1.5 1.5
Simulation Result Simulation Result
1 Equation (12) 1 Equation (12)
0.5 0.5
0 0
-0.5
-0.5 0 0.5 1 1.5 2 2.5 3 3.5 4
0 0.5 1 1.5 2 2.5 3 3.5 4
time -7
x 10
time -7
x 10
(a) (b)
Fig. 4 Numerical Solution of the Eq. (12) for Δφin= 1 rad. compared with simulation. (a) Output excess phase. (b) excess phase error.
MATLAB. Figure 4 (a) illustrates output excess phase dx 2 (t) /dt = (14)
and (b) shows the excess phase error ( 2Δϕin − x1 (t) ).
d
The simulation results show the equation mentioned in (e− at sin(bt)(−2ab − a 2 + b 2 )
(12) models the system behavior with acceptable 2πK vco
accuracy. Since (12) is a nonlinear equation, the direct +e− at cos(bt)(−a 2 + b 2 + 2ab))
solution of the system is very complicated. So we dx1 (t) /dt = (15)
introduce an approximate method. − at − at
Based on what reported in the previous works and de sin(bt)(b + a) + de cos(bt)(a − b)
many simulations performed (Fig. 4), we found out that Using bit mathematical operations, (12)-(15) can be
the output excess phase transient has a well defined combined and equation (16) is resulted; the basic
shape that can be simply approximated by an analytical trigonometric equation of the proposed method.
function. d
(e − at sin(bt)( −2ab − a 2 + b 2 ) + e − at cos(bt)( − a 2 + b 2 + 2ab))
We solve equation (12) by fitting a reasonable 2 πK vco
waveform for x1 (t) . In a BBPLL, before applying a = −α.Ip .R p (1 − tanh 2 (α.(2Δϕin − d(1 − e− at cos(bt) − e− at sin(bt)))))
phase step ( Δϕin ), the output excess phase ( x1 (t) ) is ×de−at sin(bt)(b + a) + de−at cos(bt)(a − b)
zero, according to what mentioned before, if a phase Ip
+ tanh(α.(2Δϕin − d(1 − e−at cos(bt) − e− at sin(bt))))
step enters, x1 (t) reaches a constant value ( 2Δϕin ) after Cp
the oscillatory transient and after the locking point, the (16)
final value does not change, (see Fig.4). So we consider Equation (16) holds for every time especially for the
a damping oscillatory waveform as (13) to model the special times that we have:
output excess phase. Equation (13) is the key t → ∞ ⇒ e − a.t cos(b.t) = 0 e − a.t sin(b.t) = 0 (17)
simplifying assumption that leads to straightforward
analysis along with accurate results. Equation (13) could e−at sin(bt) = −e−at cos(bt) (18)
be considered as an initial simple estimation for output
excess phase response, it is necessary to improve the − a.t
approximate solution using a simple approach. t =0⇒ e− a.t cos(b.t) = 1 e sin(b.t) = 0 (19)
Assuming this, the analysis is devoted to find d, a, and
b. The special times used above make it very simple to
find the fitting parameters. Indeed these times leave
x1 (t) = d(1 − e − at sin(bt) − e − at cos(bt)) (13) simple equations to solve.
Substituting equation (17) into (16), we can find
Regarding (12), it is necessary to find dx1 (t) /dt and
equation (20) for parameter d in term of input phase
dx 2 (t) /dt . Based on the equations indicated in (11) and step.
(13), dx 2 (t) /dt and dx1 (t) /dt can easily be obtained as
tanh(α.(2Δϕin − d)) = 0 ⇒ d = 2Δϕin (20)
(14) and (15), respectively shown at follows:
164 Iranian Journal of Electrical & Electronic Engineering, Vol. 7, No. 3, Sep. 2011when the BBPLL is locked, the final value of output To describe the transient behavior of the BBPLL, we
excess phase can be calculated by (20). need to know the features of its transient time such as
Substituting (18) into (16), a closed form equation is rise time, over shoot, peak time and settling time.
derived for parameter a in term of circuit parameters as Equation (13) is similar to the step response of a linear
second order system (see Fig. 4(a)). According to [14],
2πI p R p αK vco we can easily rewrite (13) as (26).
a= (21)
2
π
It can be seen from (21) that the parameter a is x1 (t) = d(1 − 2e− at sin(bt + )) (26)
4
directly proportional to Ip , R p , K vco and input
Using what mentioned in [14], the transient features
parameter α .
of (26) can be easily obtained as following equations.
To obtain b, we assume that the left side of (16) Rise time can be written as (27).
( dx 2 (t) /dt ) is as (22).
π−θ 3π
dx 2 (t) dx (t) 2ab + a 2 −βt tr = ⇒ tr = (27)
= 2 −d e (22) b 4b
dt new dt old 2πK vco
where θ = π/ 4 . Equation (27) shows that the rise time
In added exponential term, β is so large. This
is reversely proportional to parameter b. Also as
assumption is used to provide a proper initial condition
illustrated in [14], the peak time can be defined as (28).
for the left side of (16) (equation (14)) at t = 0 . Note
that this assumption has no effect on other equations dx1 (t) π
indicated in (20) and (21), it just leads to an appropriate tp = = 0 ⇒ tp = (28)
dt b
response for parameter b. Considering assumption of
(22) and substituting (20) in (16), we have The peak time presented in (28) is also reversely
d(b 2 − 2a 2 ) = − 2 πα.I p .R p K vco × (1 − tanh 2 (2 αΔϕ in proportional to b. And finally the over shoot is found as
I p K vco (23) x1 (t p ) − x1 (∞) −
aπ
×d(a − b) + 2 π tanh(2αΔϕin ) Mp = =e b
(29)
Cp x1 ( ∞ )
Since tanh(2αΔϕin ) ≈ 1 and knowing a and d, a
From (29), it is seen that the over shoot is function
closed-form equation for unknown parameter b can be
of a and b. If we consider the tolerance, %5, hence the
derived as (24).
settling time can be derived as (30).
2 πI K (24)
p vco
b= + 2a 2 3
dC p ts = (30)
a
It can be seen from (24), b is a function of circuit
parameters and input phase step. The settling time presented in (30) is reversely
To calculate d, a and b, we need to define the proportional to a. Resulted equations can manifest the
transient behavior of the BBPLL clearly.
parameter α . As mentioned before, tanh(2αΔϕin ) is
This method can describe the transient behavior of
approximately equal to +1 . We assume BBPLL for each input phase step and different values of
tanh(2αΔϕin ) = 0.99999 that results in (25) for design parameters. The proposed method in this paper
parameter α . can help BBPLL designers to design a BBPLL with
higher speed and more stable in transient region.
α = 3/Δϕin (25)
4 Simulation Results
For simplicity, we assumed, α only depends on the The proposed method to obtain the features of the
input step. The expression (25) can help to find a proper BBPLL is evaluated by simulations for different values
α for each value of Δϕin . The simulation results verify of input phase step Δϕin , current Ip, resistance Rp,
the accuracy of (25). capacitor Cp, and Kvco.
The closed form equations obtained in this section In this paper a BBPLL based CDR with an
can represent the unknown parameters a, d and b just Alexander PD is simulated in MATLAB simulink. A
knowing the circuit parameters and the size of phase numerical method using MATLAB software is used to
step input. solve (12) for the case that Δϕin increases. Figure 5 (a)
3.2 Transient Features of BBPLL to (d) show the numerical and approximated solution of
In previous section, we have approximated a Eq. (12), and simulated results of output excess phase,
mathematical model for output excess phase in response when Δϕin increases. Figure 5(a) to (d) show results
to phase step input. This model has been shown in (13). with different values of Δϕin = 0.8 rad, 1.0 rad, 1.2 rad
Mohseni Kolagar & Miar Naimi: Closed-Form Analytical Equations to Transient Analysis … 1652 2.5
2
1.5
Output excess phase (radian) 1.5
Output excess phase (radian)
1
1
Simulation Result
0.5 Equation (12) Simulation Result
Analytical Result 0.5 Equation (12)
Analytical Result
0
0
-0.5 -0.5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.5 1 1.5 2 2.5 3
time -7 time -7
x 10
x 10
(a) (b)
3 4
2.5 3.5
3
2
Output excess phase (radian) 2.5
Output excess phase (radian)
1.5
2
Simulation Result
1 Simulation Result 1.5 Equation (12)
Equation (12) Analytical Result
0.5 Analytical Result 1
0.5
0
0
-0.5 -0.5
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
time x 10
-7
time x 10
-7
(c) (d)
Fig. 5 Comparison between approximated and numerical results of Eq. (12) and simulation results for output excess phase when input
phase step increases. (a) Δϕ = 0.8 rad , (b) Δϕ = 1rad , (c) Δϕ = 1.2 rad , (d) Δϕ = 1.5 rad.
in in in in
and 1.5 rad, respectively. First, the value of α is Based on the presented plots and Table in this paper,
calculated for each phase step using (25). In second step the difference between precise and approximate
the unknown parameters of the estimated output are solutions for transient features is negligibly small.
calculated by (20), (21) and (24). Finally the transient Comparison between estimated and real values shows
features t r , t p , M p , and t s are calculated by (27)-(30). the accuracy of proposed equations.
Expression (25) shows, each phase step results one α ,
Table 1 Simulation parameters.
this shows that the parameter a obtained in (21) depends
on the input phase step; consequently, b is depended on
the input phase step. Therefore all important times in Simulation Parameters
transient region depend on the input phase step. Table 1
gives simulation parameters. A comparison between Resistance Rp 300Ω
estimated and real values shows the accuracy of Capacitor Cp 100pf
analytical equations. Estimated results and actual
undergoes the variation of input phase step are given in Current Ip 40uA
Table 2. The numerical, estimated and simulation VCO gain KVCO 200MHz/v
results presented in Table 2 and Figure 5 show, when
VCO Frequency 2GHz
Δϕin increases, the rise time, peak time, settling time
and over shoot increase and this is exactly what we
expect in the BBPLL.
166 Iranian Journal of Electrical & Electronic Engineering, Vol. 7, No. 3, Sep. 2011Table 2 Compparison betweenn simulation, caalculated and nuumerical resultss when input steep increases.
Calculaated Results Numerical Resu
ult Simulation Reesults
ts tp tr Mp ts tp tr Mp ts tp tr Mp Δϕ
Δ in
(μs) (μs) (μs) (μs) (μs) (μs)) (μs)
s (μs) (μs) (rad)
(
0.1 0
0.072 0.054 0.13 0.15 0.069 0.0499 0.14 0.11 0.08 0.0056 0.1 0.8
0.132 0
0.088 0.066 0.136 0.137 0.082 0.06
6 0.142 0.1336 0.094 0.0065 0.15 1
0.16 0.1 0.078 0.142 0.18 0.097 0.07
7 0.149 0.1662 0.12 0.0073 0.2 1.2
0.199 0
0.126 0.095 0.15 0.22 0.01 0.0855 0.18 0.1996 0.13 0.0085 0.23 1.5
5 Conclusionns Exp. Briefsfs, Vol. 50, N
No. 11, pp. 879-886, Nov..
This paper has presennted a novel method
m to derrive 2003.
exact enouggh analytical equations for f the transient [9]] Cessna J. R. and Levy D. M., “Phaase noise andd
response of BBPLL;
B rise time, settling time, peak time, transient times
t for a binary quan ntized digitall
and over shooot. The outpput excess phaase is assumeed a phase-lockked loop in whhite Gaussian noise”, IEEE E
damping osccillatory waveform where thhe unknowns are Trans. Com mmun., Vol. 220, No. 2, pp. 94-104, Apr..
parameters which
w result inn rise time, peeak time, settlling 1972.
time and oveer shoot. Nonlinear behavioor of the BBP PLL [10
0] Choi Y., Jeeong D.-K., annd Kim W., “Jitter
“ transferr
can be explaained easily with
w the pressented equatioons. analysis off tracked oveersampling teechniques forr
This methodd can providde insight intto BBPLL with w multigigabbit clock andd data reco overy”, IEEE E
PDs which caan help designners for better and
different BBP Trans. Cirrcuits Syst. II, Analog Digit.
D Signall
much easier designs. Process., Vol.
V 50, No. 11, pp.775-783 3, 2003.
[11
1] Chan M. and a Postula A A.,” Transiennt analysis off
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p 1571-15800, 2004. University off Technology, Babol, Mazan--
[5] Cheng S., Tong H., Silva-Martinnez J. and ˙Illker daran, Iran. She is curreently with thee
Karsılayyan A., “Steady-State Annalysis of Phaase- Inteegrated Systemms Research Labboratory, Babo ol University off
Lockedd Loops Usinng Binary Phase P Detectoor”, Tecchnology. Her research inteerest includes phase- lockedd
Trans. Circuits Syst.: Express Bieff, Vol. 54, Noo. 6, ops circuits foccused on bang--bang phase lo
loo ocked loops inn
June 20007. clock and data reecovery, monolithic clock and d data recoveryy
circcuits, and widebband amplifierss.
[6] Da Dalt N., Thaller E., E Gregorius P. and Gazsii L.,
“A com mpact triple-band low-jitterr digital LC PLLP Hossein Miaar Naimi receeived the B.Sc..
with prrogrammable coilc in 130-nm m CMOS”, IE EEE from Shariff University of Technology,,
J. Solidd-State Circuits, Vol. 40, No. 7, pp.14482- Tehran, Iran, in 1994 and th
he M.Sc. degreee
1490, Juul. 2005. from Tarbiatt Modares Univ versity, Tehran,,
[7] Da Dallt N., “Markoov chains-bassed derivationn of Iran, in 19966, and the Ph.D
D. degree from m
the phaase detector gaain in bang-baang PLLs”, IE EEE the Iran U University of Science andd
Trans. Circuits Syst.. II, Exp. Brieefs, Vol. 53, No.
N Technology, Tehran, Iran, in 2002. Sincee
2003, he has been a memberm of thee
11, pp. 1195-1199, Nov.
N 2006. Eleectrical and Electronics
E Enggineering Facu ulty of Baboll
[8] Hanum molu P., Caspeer B., Mooneyy R., Wei G. and Unniversity of Tecchnology, Mazaandaran, Babol, Iran. His res--
Moon U.,U “Analysiss of PLL clocck jitter in hiigh- earrch interests aree analog CMOS S Integrated circcuit design, RF
F
speed serial
s links”, IEEE
I Trans. Circuits Syst.. II, miccroelectronics, image processing, and ev volutional alg--
oritthms.
Mohseni Kollagar & Miarr Naimi: Closeed-Form Analy
lytical Equatio
ons to Transieent Analysis … 167You can also read
