AN13031 Recommendations for SD Connections to 1.8 V SDHC Interfaces
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AN13031
Recommendations for SD Connections to 1.8 V SDHC Interfaces
Rev. 0 — February 5, 2021 Application Note
by: NXP Semiconductors
Contents
1 Introduction 1 Introduction......................................1
2 Recommended schematics............. 1
The enhanced Security Digital Host Controller (eSDHC) in the LX216x and
3 AC timing considerations.................3
LS208xA conform to the SD Host Controller Standard Specification version
4 References...................................... 6
3.0. They are compatible with the SD Memory Card Specification version 3.01
(SDXC SDHC, SD cards), and the SDIO Card Specification version 3.0. And they are also compatible with the JESD84-B51
(eMMC/MMC cards) and JESD84-B45 respectively. The eSDHC interface can be used to get the Reset Configuration Word
(RCW), Pre-Boot Initialization (PBI), booting images from an SD card or from an eMMC. eSDHC can also be used as an interface
of storage. There is no issue for the eSDHC interface when it works with an 1.8-volt eMMC as it is an 1.8 V interface on both parts.
However, a voltage translator must be used if it interfaces with any type of SD card, such as SDXC, SDHC, and SD cards. It is the
requirement of the SD Specification Part 1 Physical Layer Specification 3.0 that the starting voltage is 3.3 V for any type of SD card.
This application note gives an example design when the eSDHC is interfaced with an SD card. Schematics for connecting to a
voltage translator will be discussed.
2 Recommended schematics
Several voltage translators on the market can be used for the eSDHC interface. NXP recommends to use NVT4857UK as it
supports High Speed (HS) and UHS-I speeds. It supports up to 208 MHz clock rate. Figure 1 shows the recommended circuit when
SDR speeds are needed.NXP Semiconductors
Recommended schematics
5 4 3 2 1
BOOTABLE SDHC1 TRANSLATION EXAMPLE
LX2160A SDHC PORT NVT4857UK TRANSLATOR SDHC CARD SOCKET
============================== ========================================== ===========================
* OVDD = EVDD = 1.8V * Keep near SDHC connector. * Card supply is fixed at 3.3V.
* Never changes. * Has internal pullups on A and B sides.
* Has ESD protection on B side, plus CD_B.
* Power Connections:
D VSD = 3.3V -- Power for LDO driving VCCB and "B" I/O cells. D
VCCA = 1.8V -- LX2160 IO power (1.8V)
VCCB = IO -- Not a power input - LDO power for IO
(3.3V @ SEL=0, 1.8V @ SEL=1) 3V3_SD
C2771 C680
3V3_SD 1.8V 1V8 2.2uF 0.1uF
C1 C2 C3 R1
0.1uF 0.1uF 2.2uF 47K J1
CONN_SD_CARD 9
A3
A2
B3
U131
SDHC1_DAT2 9
VSD
VCCA
VCCB
D2 D3 SDHC1_DAT3 1 DAT2
CLKA CLKB SDHC1_CMD 2 CD/DAT3
E2 3 CMD
U1O CLK_FB 4 VSS1
SDHC #1 PORT C1 C4 SDHC1_CLK 5 VDD G1
CMDA CMDB 6 CLK GND1 G2
CD_SW
F1 LV_SDHC1_DAT0 D1 D4 SDHC1_DAT0 7 VSS2 GND2
SDHC1_DAT0 E2 LV_SDHC1_DAT1 E1 DAT0A DAT0B E4 SDHC1_DAT1 8 DAT0
WP
SDHC1_DAT1 C1 LV_SDHC1_DAT2 A1 DAT1A DAT1B A4 DAT1
EVDD SDHC1_DAT2 C2 LV_SDHC1_DAT3 B1 DAT2A DAT2B B4
SDHC1_DAT3 DAT3A DAT3B
10
11
1V8
LV_SDHC1_CMD
GND1
GND2
E1 E3 B2
SDHC1_CMD SEL CD
D1 LV_SDHC1_CLK
SDHC1_CLK NVT4857UK
C2
C3
B2
SDHC1_DS SPI3_SCK 1V8
A3 LV_SDHC1_VSEL
OVDD SDHC1_DAT4SPI3_PCS0
4
3
2
1V8
C A4 C
SDHC1_DAT5SPI3_PCS1 B3
SDHC1_DAT6SPI3_PCS2 C3
SDHC1_DAT7SPI3_PCS3
U2
1
R0.07D - 15 of 23 PRTR5V0U2AX
PLX2160PC72229B + HW ASSEMBLY, FAN-HEATSINK
LX2160A I2C PORT
=================
OVDD = 1.8V CLOCK FEEDBACK
U132L ==========================
I2C PORTS * Clock feedback is optional
F5 but recommended if possible.
IIC1_SCL G5
IIC1_SDA
E3
IIC2_SCL E4
IIC2_SDA
H5
CD/WP NOTES
IIC3_SCL J5 ==================================
IIC3_SDA * CD_B has a pullup and ESD protection (to VCCA)
K5
in the NVT4857U. WP does not so requires external
IIC4_SCL L5 components.
IIC4_SDA
* CD_B is optional in some cases, except when SDHC1
C4
is used as a boot source.
(IIC5_SCL) SPI3_SOUT
D3 LV_SDHC1_CLK_SYNC_IN * The LX2160A CD_B pin must be low to boot from SDHC1,
(IIC5_SDA) SPI3_SIN
B
either from the slot or direct pulldown. B
D27
* For non-bootable SDHC1, refer to the design checklist
IIC6_SCL C27 for other CD_B options.
IIC6_SDA
* WP is completely optional.
R0.07D - 12 of 23
PLX2160PC72229B + HW ASSEMBLY, FAN-HEATSINK
OPTIONAL
3V3 3V3_SD
R2 0
DNP
U3
NX5P3090UK
B1 C2
B2 VINT1 VBUS1 D1
C1 VINT2 VBUS2 D2
VINT3 VBUS3
A2 A3
FAULT ILIM
GND1
GND2
GND3
PORESET_B A1
EN R3
-
47K
C2772
B3
C3
D3
0.1uF
OPTIONAL OPTION
2
A A
1 Q53
PMV65XP
SDHC CARD RESET NOTES
=========================
* SDHC cards do not have reset pins, to exit HS modes 3
a power cycle is required. R4
Classification: Public Information
* A power supply/power gate controlled by PORESET_B 33 Drawing Title:
is used such that power is active when PORESET_B EXAMPLE
is not asserted. Page Title:
* A FET to clamp SD voltage quickly MAY be needed if
LX2160: SDHC1 EXAMPLE
the reset signal is of short duration, or excessive
capacitance is present. Size Document Number Rev
C n/a C
Date: Tuesday, November 17, 2020 Sheet 1 of 63
5 4 3 2 1
Figure 1. Recommended voltage translator schematics
The SD card signaling voltage is 1.8 V when it is configured to run at an SDR speed. Based on the SD specification, once signal
voltage is swithced to 1.8 V, the card continues 1.8 V signalling regardless of CMD0. Power cycle reset the signal voltage to 3.3
V. Therefore, a period of power-off is needed for the SD after a reset.
The power-off design can be avoided if HS mode can meet system requirements. Figure 2 shows the recommended circuit when
only HS speed is needed. In this case, no power-off SD card circuit is needed as the signaling voltage runs at 3.3 V.
Recommendations for SD Connections to 1.8 V SDHC Interfaces, Rev. 0, February 5, 2021
Application Note 2/7NXP Semiconductors
AC timing considerations
5 4 3 2 1
BOOTABLE SDHC1 TRANSLATION EXAMPLE 2
LX2160A SDHC PORT NVT4857UK TRANSLATOR SDHC CARD SOCKET
============================== ========================================== ===========================
* OVDD = EVDD = 1.8V * Keep near SDHC connector. * Card supply is fixed at 3.3V.
* Never changes. * Has internal pullups on A and B sides.
* Has ESD protection on B side, plus CD_B.
* Power Connections:
D VSD = 3.3V -- Power for LDO driving VCCB and "B" I/O cells. D
VCCA = 1.8V -- LX2160 IO power (1.8V)
VCCB = IO -- Not a power input - LDO power for IO
(3.3V @ SEL=0, 1.8V @ SEL=1) 3V3_SD
C2771 C680
3V3_SD 1.8V 1V8 2.2uF 0.1uF
C1 C2 C3 R1
0.1uF 0.1uF 2.2uF 47K J1
CONN_SD_CARD 9
A3
A2
B3
U131
SDHC1_DAT2 9
VSD
VCCA
VCCB
D2 D3 SDHC1_DAT3 1 DAT2
CLKA CLKB SDHC1_CMD 2 CD/DAT3
E2 3 CMD
U1O CLK_FB 4 VSS1
SDHC #1 PORT C1 C4 SDHC1_CLK 5 VDD G1
CMDA CMDB 6 CLK GND1 G2
CD_SW
F1 LV_SDHC1_DAT0 D1 D4 SDHC1_DAT0 7 VSS2 GND2
SDHC1_DAT0 E2 LV_SDHC1_DAT1 E1 DAT0A DAT0B E4 SDHC1_DAT1 8 DAT0
WP
SDHC1_DAT1 C1 LV_SDHC1_DAT2 A1 DAT1A DAT1B A4 DAT1
EVDD SDHC1_DAT2 C2 LV_SDHC1_DAT3 B1 DAT2A DAT2B B4
SDHC1_DAT3 DAT3A DAT3B
10
11
1V8
LV_SDHC1_CMD
GND1
GND2
E1 E3 B2
SDHC1_CMD SEL CD
D1 LV_SDHC1_CLK
SDHC1_CLK NVT4857UK
C2
C3
B2
SDHC1_DS SPI3_SCK 1V8
A3 LV_SDHC1_VSEL
OVDD SDHC1_DAT4SPI3_PCS0
4
3
2
1V8
C A4 C
SDHC1_DAT5SPI3_PCS1 B3
SDHC1_DAT6SPI3_PCS2 C3
SDHC1_DAT7SPI3_PCS3
U2
1
R0.07D - 15 of 23 PRTR5V0U2AX
PLX2160PC72229B + HW ASSEMBLY, FAN-HEATSINK
LX2160A I2C PORT
=================
OVDD = 1.8V CLOCK FEEDBACK
U132L ==========================
I2C PORTS * Clock feedback is optional
F5 but recommended if possible.
IIC1_SCL G5
IIC1_SDA
E3
IIC2_SCL E4
IIC2_SDA
H5
CD/WP NOTES
IIC3_SCL J5 ==================================
IIC3_SDA * CD_B has a pullup and ESD protection (to VCCA)
K5
in the NVT4857U. WP does not so requires external
IIC4_SCL L5 components.
IIC4_SDA
* CD_B is optional in some cases, except when SDHC1
C4
is used as a boot source.
(IIC5_SCL) SPI3_SOUT
D3 LV_SDHC1_CLK_SYNC_IN * The LX2160A CD_B pin must be low to boot from SDHC1,
(IIC5_SDA) SPI3_SIN
B
either from the slot or direct pulldown. B
D27
* For non-bootable SDHC1, refer to the design checklist
IIC6_SCL C27 for other CD_B options.
IIC6_SDA
* WP is completely optional.
R0.07D - 12 of 23
PLX2160PC72229B + HW ASSEMBLY, FAN-HEATSINK
A A
Classification: Public Information
Drawing Title:
EXAMPLE
Page Title:
LX2160: SDHC1 EXAMPLE
Size Document Number Rev
C n/a C
Date: Tuesday, November 17, 2020 Sheet 1 of 63
5 4 3 2 1
Figure 2. Recommended voltage translator schematics without resetting SD card circuit
As you can see from Figure 1 and Figure 2, the difference between these two designs is the power-off circuit. The design of this
circuit should meet the SD specification requirement of keeping power level less than 0.5 V and more than 1 ms.
3 AC timing considerations
eSDHC interface on LX2160xA supports both SDR50 and DDR50 modes. This section gives the AC timing specifications for
SDR50 and DDR50 based on the recommended NVT4857UK part.
Table 1 provides the eSDHC AC timing specifications for SDR50 mode.
Table 1. eSDHC SDR50 mode AC timing specifications with a voltage translator
Parameter Symbol1 Min. Max. Unit Notes
SDHC_CLK clock frequency fSHSCK 0.0 100.0 MHz —
tSHSCKR/
SDHC_CLK rise and fall times — 2.0 ns 2
tSHSCKF
SDHC_CLK duty cycle tSHSCK 47.0 53.0 % 3
Input setup times
(SDHC_CMD, SDHC_DATx to tSHSIVKH 1.9 — ns 2, 4, 5
SDHC_CLK_SYNC_IN),
Table continues on the next page...
Recommendations for SD Connections to 1.8 V SDHC Interfaces, Rev. 0, February 5, 2021
Application Note 3/7NXP Semiconductors
AC timing considerations
Table 1. eSDHC SDR50 mode AC timing specifications with a voltage translator (continued)
Parameter Symbol1 Min. Max. Unit Notes
Input hold times
(SDHC_CMD, SDHC_DATx to tSHSIXKH 0.7 — ns 2, 4, 5
SDHC_CLK_SYNC_IN)
Output hold time (SDHC_CLK to 2, 5, 6
tSHSKHOX 1.6 — ns
SDHC_CMD, SDHC_DATx valid)
Output delay time (SDHC_CLK to 2, 5, 6
tSHSKHOV — 5.7 ns
SDHC_CMD, SDHC_DATx valid)
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC
highspeed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O)
reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. CCARD ≤ 10 pF, (1 card), and CL = CBUS + CHOST + CCARD ≤ 30 pF.
3. Sampled and not 100% tested
4. See Figure 3
5. The voltage translator parameters are based on:
• Channel-to-channel skew is min -0.5 ns, max +0.5 ns.
• CLK_Feedback to DAT/CMD delay is min -0.5 ns, max +0.5 ns.
6. See Figure 4
Figure 3 provides the eSDHC input AC timing diagram for SDR50 mode.
T CLK
SDHC_CLK_SYNC_IN
TSHSIVKH TSHSIXKH
SDHC_CMD/
SDHC_DAT
input
Figure 3. eSDHC SDR50 mode input AC timing diagram
Figure 4 provides the eSDHC output timing diagram for SDR50 mode.
Recommendations for SD Connections to 1.8 V SDHC Interfaces, Rev. 0, February 5, 2021
Application Note 4/7NXP Semiconductors
AC timing considerations
T
CLK
SD_CLK
T
SHSKHOV
SDHC_CMD/SDHC_CMD_DIR
SDHC_DAT/SDHC_DATn_DIR
output
T
SHSKHOX
Figure 4. eSDHC SDR50 mode output timing diagram
Table 2 provides the eSDHC AC timing specifications for DDR50 mode with a voltage translator.
Table 2. SDHC AC timing specifications for DDR50 mode with a voltage translator
Parameter Symbol1 Min. Max. Unit Notes
SDHC_CLK clock frequency fSHCK 0.0 50.0 MHz 2
tSHCKR/
SDHC_CLK rise and fall times — 4.0 ns 2, 3
tSHCKF
SDHC_CLK duty cycle tSHCK 47.0 53.0 % 2, 4
Input setup times (SDHC_DATx to 2, 3, 5, 6
tSHDIVKH 1.6 — ns
SDHC_CLK_SYNC_IN)
Input hold times (SDHC_DATx to 2, 3, 5, 6
tSHDIXKH 0.7 — ns
SDHC_CLK_SYNC_IN)
Output hold time (SDHC_CLK to 2, 3, 6, 7
tSHDKHOX 2.2 — ns
SDHC_DATx valid)
Output delay time (SDHC_CLK to 2, 3, 6, 7
tSHDKHOV — 5.6 ns
SDHC_DATx valid)
Input setup times (SDHC_CMD to 2, 3, 5, 6
tSHCIVKH 4.8 — ns
SDHC_CLK_SYNC_IN)
Input hold times (SDHC_CMD to 2, 3, 5, 6
tSHCIXKH 0.7 — ns
SDHC_CLK_SYNC_IN)
Output hold time (SDHC_CLK to 2, 3, 6, 7
tSHCKHOX 2.2 — ns
SDHC_CMD valid)
Output delay time (SDHC_CLK to 2, 3, 6, 7
tSHCKHOV — 12.6 ns
SDHC_CMD valid)
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSHKHOX symbolizes eSDHC
highspeed mode device timing (SH) clock reference (K) going to the high (H) state, with respect to the output (O)
reaching the invalid state (X) or output hold time. Note that in general, the clock reference symbol is based on five letters
Recommendations for SD Connections to 1.8 V SDHC Interfaces, Rev. 0, February 5, 2021
Application Note 5/7NXP Semiconductors
References
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the appropriate
letter: R (rise) or F (fall).
2. CL = CBUS + CHOST + CCARD ≤ 25pF for Input Data of DDR50, ≤ 30pF for Input CMD of DDR50.
3. CCARD ≤ 10 pF, (1 card)
4. Sampled and not 100% tested
5. See eSDHC DDR50/DDR mode input AC timing diagram in QorIQ LX2162A/LX2122A/LX2082A Data Sheet.
6. The voltage translator parameters are based on:
• Channel-to-channel skew is min -0.5 ns, max +0.5 ns.
• CLK_Feedback to DAT/CMD delay is min -0.5 ns, max +0.5 ns.
7. See eSDHC DDR50/DDR mode output AC timing diagram in QorIQ LX2162A/LX2122A/LX2082A Data Sheet.
4 References
SD Specifications, Part 1, Physical Layer Specification Version 3.01
QorIQ LX216xA Data Sheet, where x can be either 0 or 2
QorIQ LS20xyA Data Sheet, where x can be either 8 or 4, y can be 0, 1, 4 or 8
QorIQ LS2088A Reference Manual
QorIQ LX2160A Reference Manual
QorIQ LX2162A Reference Manual
JESD84-B51, Embedded Multi-Media Card (eMMC) Electrical Standard (5.1)
Recommendations for SD Connections to 1.8 V SDHC Interfaces, Rev. 0, February 5, 2021
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Date of release: February 5, 2021
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