Advanced Program 2021 International Conference on Analog VLSI Circuits (AVIC 2021)
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2021 International Conference on
Analog VLSI Circuits (AVIC 2021)
Bordeaux, France, 18th–21st Oct. 2021
Advanced Program
Organised & Sponsored by
Institute of Electrical Engineers of Japan
International Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
Message from General Co-Chair
The International Conference on Analog VLSI Circuits or AVIC is the successor of International
Analog VLSI Workshop, which had been held for more than 20 years. The workshop was initiated
by the Research Committee on Electronic Circuits of the Institute of Electrical Engineers of Japan
(IEEJ). The first workshop was inaugurated in 1997, in Columbus, Ohio, USA. Since then it has been
organized by incorporating with a selected host country each year.
Like the workshop, the purpose of the AVIC is to provide the international stage for students, re-
searchers, professors, and industrial specialists in the field of analog VLSI, to exchange ideas and
recent research results, as well as their applications. It has contributed to long-standing worldwide
community of analog VLSI circuit experts in industry and academia.
In this time, we are happy to open AVIC 2021 in Bordeaux of France in spite of the difficult situation
due to COVID-19. AVIC in Bordeaux is second time, the first was held in 2005. Many thanks to all
the professors and researchers who have supported to AVIC, the second AVIC in Bordeaux has been
realized. We are honored to be the general co-chair in this time.
Thank all friends from Japan, France and other countries who have been supporting us to organize
the conference. Thank all members of the organizing committee for their hard works.
Last but not least, on behalf of the organizing committee, we would like to express our appreciation to
every participant joining the AVIC 2021 conference. Without your support, staging of this conference
would not have been possible.
Welcome everyone to Bordeaux on-site and on-line, to 2021 International Conference on Analog VLSI
Circuits. Let’s have a good time here together.
Prof. Dr. François Rivet Prof. Dr. Kawori Sekine
Université de Bordeaux, France Meiji University, Japan
i
International Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
Message from Technical Program Committee Chair
On behalf of the Technical Program Committee, we are pleased to welcome you to AVIC 2021.
AVIC 2021’s technical program covers topics of wide area about not only analog circuit technology
but related technical issues. The Technical Program Committee selected 43 papers to be presented at
AVIC 2021.
Papers are organized into following 9 topics. “Emerging Communication System”, “RF Wireless/Filter”,
“Analog-to-Digital Converter (ADC)”, “Low Noise Amplifier (LNA)”, “Digital-to-Analog Converter
(DAC)”, “Neural Network/Machine Learning”, “RO/PLL”, “Integrated Circuit Technology”, “Energy
Harvesting/Voltage Converter”. AVIC 2021 also features three keynotes and two invited talks. These
keynote/invited talks cover the latest microelectronics topics and electronic applications.
We would like to take this opportunity to express our most sincere thanks to all authors who have
submitted manuscripts to this conference. Your participation and contribution attest the vibrant
energy, excitement, and creativity exhibited by this growing electoronics circuit community. We
would like to thank the technical program committee members for their hard work providing objective,
unbiased, and timely reviews for each submitted manuscript. We would also like to express our sincere
appreciation of the leadership and diligent work of our 9 track chairs for TPC member recruitment,
coordination of review process, session organization, and technical program compilation.
Last, but certainly not the least, we are very grateful to the international advisors of the technical
program for their advice and encouragement through out the process.
Welcome to Bordeaux, France. We hope you will enjoy the AVIC 2021 technical program as much as
we do.
Mr. Satoru Shingai
Canon Inc., Japan
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International Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
Organizing Committee
General Co-Chairs François Rivet, Université de Bordeaux
Kawori Sekine, Meiji University
General Co-secretaries Marina Deng, Université de Bordeaux
Kazuyuki Wada, Meiji University
Technical Program Committee Chair Satoru Shingai, Canon Inc.
Technical Program Committee Secretarie Ryo Kishida, Tokyo University of Science
Financial Co-Chairs Magali De Matos, Université de Bordeaux
Hiroki Sato, Tokyo Institute of Technology
Tomochika Harada, Yamagata University
Publication Co-Chairs Patricia Desgreys, Telecom ParisTech
Yasuhiro Takahashi, Gifu University
Nicodimus Retdian, Shibaura Institute of Technology
Publicity Co-Chairs Eric Kerhervé, Université de Bordeaux
Hao San, Tokyo City University
Local Arrangement Chair Nathalie Deltimple, Université de Bordeaux
Chhandak Mukherjee, Université de Bordeaux
Liaison Co-Chairs Yann Deval, Université de Bordeaux
Andrei Vladimirescu, University of California, Berkeley
Advisory Board Shigetaka Takagi, Tokyo Institute of Technology
Akira Hyogo, Tokyo University of Science
iiiInternational Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
Conference Time Table
Time: France Time Zone (Central European Summer Time, UTC+2)
Monday Tuesday Wednesday Thursday
October 18th October 19th October 20th October 21st
8:15–8:30
Opening Ceremony
8:30–9:30 8:30–9:30 9:00–10:00 9:00–12:00
Keynote 1 Keynote 2 Keynote 3 Student Event
Dr. Ryuichi Fujimoto Dr. Keith O’Donoghue Dr. Victor Grimblatt
9:30–11:30 9:30–11:30 10:00–12:00 12:00–12:30
Session A Session B Session C Closing
Session A.1 Session B.1 Session C.1 &
Session A.2 Session B.2 Session C.2 Award Ceremony
11:30–12:00 11:30 - 12:00
Invited 1 Invited 2
Prof. Edoardo Charbon Prof. Jan Rabaey
12:00–14:00 12:00–14:00 12:00–14:00
Lunch Lunch Lunch
14:30–17:30 14:30–17:30 14:00–18:15
BEE Week BEE Week BEE Week
17:30–19:30 17:30–23:00
Welcome Reception Cultural Event
&
Gala Dinner
All magenta text is a link to the virtual conference site (Zoom and YouTube). If the pdf viewer blocks
these hyperlinks, allow links to the internet in viewer.
ivInternational Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
Keynote
Monday October 18th 8:30–9:30
Chairman: Prof. Kawori Sekine
Speaker Dr. Ryuichi Fujimoto, Kioxia Corp.
Title Technical challenges toward high-bandwidth and large-capacity storages with low-
power consumption
Abstract Recently, big data analysis such as machine learning has become familiar to our life, high-
performance computing (HPC) with low-power consumption is one of essential technology for
such applications. Not only high-performance processors such as CPUs, GPUs, and FPGAs, but
also high-performance memories and storages are very important for the HPC. In this paper,
some techniques toward high-bandwidth and large-capacity storages using NAND flash memories
are introduced. Basically, a high-speed interface is needed for high-bandwidth performance, and
we have developed a bridge chip with a high-speed serial interface applying to NAND flash
memories. The large capacities of storages are simultaneously achieved by using the bridge
chips with daisy-chain connections. In view of the low-power consumption, co-optimization
design between a transceiver for the high-speed interface and transmission lines on printed
circuit boards (PCBs) is important. Therefore, precise design techniques are also presented
for low-power consumption.
Biography Dr. Ryuichi Fujimoto is senior fellow of Kioxia corporation. He was engaged in the
research and development of integrated circuits and device modeling for various wireless com-
munication systems in Toshiba corporation. After belonging to Kioxia corporation, he manages
research and development of high-performance interfaces for NAND flash memories. Dr. Fuji-
moto was a chair of the Japan chapter of IEEE solid-state circuits society.
Tuesday October 19th 8:30–9:30
Chairman: Prof. François Rivet
Speaker Dr. Keith O’Donoghue, Director of Engineering, Qualcomm
Title Precision analog design challenges on “Big Digital” SoC
Biography Dr. Keith O’Donoghue is Director of Engineering of the Analog/Mixed-Signal IP design
team at Qualcomm, Cork, Ireland since 2018. He received the B.Eng. and M.Eng.Sc. degrees in
Microelectronic Engineering from University College Cork in 2004 and 2005 respectively and the
Ph.D. degree in Electrical and Computer Engineering from the University of California at Davis
in 2009 in the area of switched-capacitor sigma-delta ADCs. From 2009 to 2018 he worked as an
Analog/RF IC Design Engineer on various low-power mixed-signal products for both Cypress
Semiconductor and Analog Devices. He has 6 granted U.S. patents in the area of precision
AFEs and data converter systems and is currently a Visiting Lecturer at University College
Cork, Ireland where he is teaching a graduate level course in Data Converter IC Design.
vInternational Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
Wednesday October 20th 9:00–10:00a
Chairman: Prof. Patricia Desgreys
Speaker Dr. Victor Grimblatt, R&D Group Director and General Manager, Synopsys
Title Thinking outside the CMOS box
Biography Dr. Victor Grimblatt has an engineering diploma in microelectronics from Institut Na-
tionale Polytechnique de Grenoble (INPG – France) and an electronic engineering diploma from
Universidad Tecnica Federico Santa Maria (Chile). He is doing his PhD on IoT for Smart Agri-
culture at IMS lab, University of Bordeaux. He is currently R&D Group Director and General
Manager of Synopsys Chile. He has expertise and knowledge in business and technology and un-
derstands very well the trends of the electronic industry; therefore, he is often consulted for new
technological business development. He has published several papers in IoT, EDA and embedded
systems development, and since 2007 he has been invited to several Latin American Conferences
(Argentina, Brazil, Chile, Mexico, Peru and Uruguay) to talk about Circuit Design, EDA, IoT,
and Embedded Systems. Since 2012 he is chair of the IEEE Chilean chapter of the CASS. He is
also the President of the Chilean Electronic and Electrical Industry Association (AIE). He has
been part of several conferences TCP (ISCAS, ICECS, LASCAS) and is chairing the EDA and
Circuit design Sub-Committee for ICECS. He is also is Program Co-Chair of FoodCAS. Since
2018 he is Chair of LASCAS Steering Committee.
a
This keynote is sponsored by IEEE CAS France chapter.
viInternational Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
Invited Talk
Monday October 18th 11:30–12:00
Chairman: Prof. Jean Baptiste Begueret
Speaker Prof. Edoardo Charbon, EPFL
Title Cryo-CMOS quantum control: from a wild idea to working silicon
Abstract The core of a quantum processor is generally an array of qubits that need to be controlled
and read out by a classical processor. This processor operates on the qubits with nanosecond
latency, several millions of times per second, with tight constraints on noise and power. This is
due to the extremely weak signals involved in the process that require highly sensitive circuits
and systems, along with very precise timing capability. We advocate the use of CMOS technolo-
gies to achieve these goals, whereas the circuits will be operated at deep-cryogenic temperatures.
We believe that these circuits, collectively known as cryo-CMOS control, will make future qubit
arrays scalable, enabling a faster growth in qubit count. In the lecture, the challenges of design-
ing and operating complex circuits and systems at 4K and below will be outlined, along with
preliminary results achieved in the control and read-out of qubits by ad hoc integrated circuits
that were optimized to operate at low power in these conditions. The talk will conclude with a
perspective on the field and its trends.
Biography Prof. Edoardo Charbon (SM’00–F’17) received the Diploma from ETH Zurich, the M.S.
from the University of California at San Diego, and the Ph.D. from the University of California
at Berkeley in 1988, 1991, and 1995, respectively, all in electrical engineering and EECS. He has
consulted with numerous organizations, including Bosch, X-Fab, Texas Instruments, Maxim,
Sony, Agilent, and the Carlyle Group. He was with Cadence Design Systems from 1995 to 2000,
where he was the Architect of the company’s initiative on information hiding for intellectual
property protection. In 2000, he joined Canesta Inc., as the Chief Architect, where he led
the development of wireless 3-D CMOS image sensors. Since 2002 he has been a member of
the faculty of EPFL. From 2008 to 2016 he was with Delft University of Technology’s as full
professor and Chair of VLSI design. He has been the driving force behind the creation of
deep-submicron CMOS SPAD technology, which is mass-produced since 2015 and is present in
telemeters, proximity sensors, and medical diagnostics tools. His interests span from 3-D vision,
LiDAR, FLIM, FCS, NIROT to super-resolution microscopy, time-resolved Raman spectroscopy,
and cryo-CMOS circuits and systems for quantum computing. He has authored or co-authored
over 400 papers and two books, and he holds 23 patents. Dr. Charbon is a distinguished visiting
scholar of the W. M. Keck Institute for Space at Caltech, a fellow of the Kavli Institute of
Nanoscience Delft, a distinguished lecturer of the IEEE Photonics Society, and a fellow of the
IEEE.
Tuesday October 19th 11:30–12:00
Chairman: Prof. Andrei Vladirimescu
Speaker Prof. Jan Rabaey, University of California, Berkeley
Title Sensing to action – The future of distributed intelligence
viiInternational Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
Regular Session
Monday October 18th 9:30–11:30
Session A1: “Emerging Communication System” and “RF Wireless/Filter”
Chairman: Prof. Guillaume Ferré
A1.1 Which solid-state process for 6G challenge
Didier Belot∗ , Emilio Calvanese-Strinati, Jean-Baptiste Doré (CEA)
A1.2 NAASC cubeSat phase 0 radio frequencies link budget
Axel Miqueau∗ , Théo Dubasque, Guillaume Ferré, Anthony Ghiotto (Enseirb-Matmeca)
A1.3 An IoT-based system to enforce COVID-19 health regulations dedicated to student traffic con-
trol in higher education areas
Rémi Quéheille∗ (Bordeaux INP, IMS Lab.); Emmanuel Pages (Bordeaux INP); Francois Rivet,
Guillaume Ferre (Université de Bordeaux)
A1.4 Social distancing estimation using an IoT-based system and Bluetooth signal detection
Maxandre Fellmann∗ (Bordeaux INP); Francois Rivet (Université de Bordeaux); Maxime Le Gall,
Guillaume Ferre, Eric Kerherve (Bordeaux INP)
A1.5 A Maximum bit rate formulation and design method of FSK-based simultaneous wireless power
and data transfer circuit
Takahiro Fujita∗ , Kazuyuki Wada (Meiji University)
A1.6 Study on the feasibility of a NB-IoT receiver using N-path circuits
Corentin Delignac∗ (IMS Lab.); Léo Lançon, Salime Boumlik (IMS Lab., NXP Semiconductors)
A1.7 A low-cost IoT-based device to measure exposure to sub-6GHz 5G waves
Louis Guénégo∗ , Anouar Walzik, Aharram Souhayl, Amine Karbab, Guillaume Ferre (IMS
Lab.); Francois Rivet (Université de Bordeaux)
A1.8 Proof-of-concept of a COTS arbitrary waveform generator using orthogonal sequences
Rémi Quéheille∗ (Bordeaux INP, IMS Lab.); Francois Rivet (Université de Bordeaux); Nathalie
Deltimple (IMS Lab.); Yann Deval (Université de Bordeaux); Eric Kerherve (IMS Lab.)
Session A2: Analog-to-Digital Converter (ADC)
Chairman: Prof. Hao San
A2.1 Folding ADC for multi-bit ∆Σ AD modulator
Xiongyan Li∗ , Tianrui Feng, Lengkhang Nengvang, Shogo Katayama, Jianglin Wei (Gunma
University); Haijun Lin (Xiamen Institute of Technology); Kazufumi Naganuma, Kiyoshi Sasai,
Junichi Saito (Alps Alpine Co., Ltd.); Anna Kuwana, Haruo Kobayashi (Gunma University)
A2.2 Second-order delta-sigma down-converting ADC with even harmonic mixer and noise-shaping
dynamic element matching
Yuki Genkaku∗ , Akira Yasuda, Michitaka Yoshino, Syuji Okage (Hosei University)
A2.3 Dynamic element matching for successive approximation register and delta-sigma modulator
two-step analog-to-digital converter with digital-to-analog converter and residual gain error
Rei Watanabe∗ , Akira Yasuda, Michitaka Yoshino (Hosei University)
A2.4 Designing opamp amplifiers for a 5th order CT CRFF ∆Σ ADC using model-based design
paradigm and gm/ID methodology
Abderrahmane Ghimouz∗ (Université Grenoble Alpes, Grenoble INP, CNRS, LPSC-IN2P3)
viiiInternational Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
A2.5 An 8-bit hybrid analog-to-digital converter combining flash with radix-3 and two-bit/cycle suc-
cessive approximation resister analog-to-digital converter
Ryukichi Hirai∗ , Ryo Kishida, Tatsuji Matsuura, Akira Hyogo (Tokyo University of Science)
A2.6 Code selective histogram method: Two-tone signal for ADC linearity test time reduction
Yujie Zhaoi∗ , Anna Kuwana, Shogo Katayama, Jianglin Wei, Haruo Kobayashi, Takayuki
Nakatani, Kazumi Hatayama (Gunma University); Keno Sato, Takashi Ishida, Toshiyuki Okamoto,
Tamotsu Ichikawa (ROHM Co., Ltd.)
A2.7 Two-step incremental ADC architecture with self-calibration of two reference voltages ratio
Lengkhang Nengvang∗ , Shogo Katayama, Jianglin Wei, Lei Sha, Tri Minh Tran (Gunma Uni-
versity); Kazufumi Naganuma, Kiyoshi Sasai, Junichi Saito (Alps Alpine Co., Ltd.); Anna
Kuwana, Haruo Kobayashi (Gunma University)
Tuesday October 19th 9:30–11:30
Session B1: “Low Noise Amplifier (LNA)” and “Digital-to-Analog Converter (DAC)”
Chairman: TBA.
B1.1 A multichannel front-end electronics ASIC for high-accuracy time measurements using diamond
detectors
Abderrahmane Ghimouz∗ (Université Grenoble Alpes, Grenoble INP, CNRS, LPSC-IN2P3)
B1.2 3.4 to 4.1 GHz wideband LNA with gain flatness and low noise figure
Dai Yoshioka∗ , Takayuki Morisita, Kiyotaka Komoku, Nobuyuki Itoh (Okayama Prefectural
University)
B1.3 1.65/2.5/4.0-GHz triple-band concurrent low-noise amplifier
Shinichiro Seguchi∗ , Takayuki Morishita, Kiyotaka Komoku, Nobuyuki Itoh (Okayama Prefec-
tural University)
B1.4 920 MHz low-power LNAs operated in moderate inversion region
Kazuya Miyazaki∗ , Takayuki Morishita, Kiyotaka Komoku, Nobuyuki Itoh (Okayama Prefectural
University)
B1.5 DA conversion circuit employed for digital delay control of analog FIR filters
Koki Kinoshita∗ , Kawori Sekine (Meiji University)
B1.6 Segmented DAC unit cell selection algorithm and layout/routing based on Euler’s knight tour
Dan Yao∗ , Xueyan Bai, Anna Kuwana, Kazuyuki Kawauchi, Masashi Higashino, Haruo Kobayashi
(Gunma University); Akira Suzuki, Satoshi Yamada, Tomoyuki Kato, Nobuto Ono, Kazuhiro
Miura, Kouji Hirai , Ritsuko Kitakoga (JEDAT Inc.)
B1.7 Design of digital-to-analog converter architectures based on polygonal numbers
Xueyan Bai∗ , Dan Yao, Yuanyang Du, Minh Tri Tran, Anna Kuwana, Haruo Kobayashi
(Gunma University); Kazuyoshi Kubo (National Institute of Technologoy, Oyama College)
Session B2: Neural Network/Machine Learning
Chairman: TBA.
B2.1 Analog circuit synthesis using multi-label classification
Ryo Sako∗ , Nobukazu Takai (Gunma University)
ixInternational Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
B2.2 Automatic synthesis of operational amplifier by learning of gate connections using genetic al-
gorithm
Hiroki Kato∗ , Nobukazu Takai, Satoshi Konno (Gunma University)
B2.3 Portable brain speller: A low-complexity 1D-CNN architecture for embedded platform applica-
tions
Giovanni Mezzina∗ , Filippo Dimauro (Politecnico di Bari); Daniela De Venuto (NIL)
B2.4 Filter design for power supply circuits independent of the transfer function of the control target
using deep learning
Naoya Hasunuma∗ , Nobuhiko Nagashima, Nobukazu Takai (Gunma University)
B2.5 A pulse-type hardware chaotic neural network with gap junctions for IC implementation
Takuto Yamaguchi, Katsutoshi Saeki∗ , Yoshiki Sasaki (Nihon University)
B2.6 A pulse-type hardware chaotic neuron device with a negative resistance control circuit imple-
mented using a 0.18 µm CMOS process
Yoshiki Sasaki∗ , Katsutoshi Saeki (Nihon University)
B2.7 Analog history storage circuit for ultrafast photonic reinforcement learning
Kai Ichikawa∗ , Kawori Sekine, Kazuyuki Wada (Meiji University); Shinsuke Hara, Akifumi
Kasamatsu, Satoru Tanoi (NICT); Makoto Naruse (The University of Tokyo)
B2.8 Tolerance analysis of comparator for ultrafast photonic reinforcement learning
Hiroki Iwahara∗ , Kawori Sekine, Kazuyuki Wada (Meiji University); Shinsuke Hara, Akifumi
Kasamatsu, Satoru Tanoi, Ruibing Dong (NICT); Makoto Naruse (The University of Tokyo)
Wednesday October 20th 10:00–12:00
Session C1: “RO/PLL” and “Integrated Circuit Technology”
Chairman: Dr. Didier Belot
C1.1 Ultra low power injection-locked ring oscillator architecture using FDSOI technology
Yuqing Mao∗ , Yoann Charlon Florian Debieu, Zhaopeng Wei, Yves Leduc, Gilles Jacquemod
(Université Côte d’Azur)
C1.2 0.18 µm CMOS ring oscillator: NBTI and HCI modelling for long-term stress
Yen Thi Phuong Tran∗ (Université de Bordeaux), Toshihiro Nomura, Mohamed Salim Cherchali,
Claire Tassin (Etudes et Production Schlumberger); Yann Deval, Cristell Maneux (Université
de Bordeaux)
C1.3 A 1.6 Gbps phase-locked-loop with injection-locked ring oscillator for SerDes application
Dorian Vert∗ (Université de Bordeaux), Michel Pignol (CNES); Vincent Lebre (Thales Ale-
nia Space); Emmanuel Moutaye (Thales Alenia Space); Florence Malou (CNES); Jean-Baptiste
Begueret (Université de Bordeaux)
C1.4 A 138 Vpp amplitude and drivability tunable ultrasound pulser for a 3072 ch matrix probe
Toru Yazaki∗ , Yutaka Igarashi, Takuma Nishimoto, Shinya Kajiyama, Yusaku Katsube (Hitachi,
Ltd.); Yoshihiro Hayashi, Takuya Kaneko (FUJIFILM Healthcare Co.)
C1.5 Design consideration on MOS peaking current sources insensitive to supply voltage and tem-
perature
Takahumi Kamio∗ , Takashi Hosono, Souma Yamamoto, Jun-ichi Matsuda, Shyougo Katayama,
Anna Kuwana (Gunma University); Akira Suzuki, Satoshi Yamada, Tomoyuki Kato, Nobuto
Ono, Kazuhiro Miura (JEDAT Inc.); Haruo Kobayashi (Gunma University)
xInternational Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
C1.6 Analog-to-feature converter optimization through power-aware feature selection
Antoine Back∗ , Paul Chollet, Olivier Fercoq, Patricia Desgreys (Télécom Paris)
C1.7 Analyse and design of a capacitive-isolation-based information transmission system
Ming Zhang∗ (Université Paris-Saclay); Nicolas Llaser (DORIAN)
C1.8 First extraction of thermal contribution in 3D vertical junctionless nanowire transistors
Bixente Burucoa∗ , Lucas Réveil, Chhandak Mukherjee, Marina Deng, Cristell Maneux (IMS
Lab., Université de Bordeaux); Abhishek Kumar, Aurélie Lecestre, Guilhem Larrieu (LAAS-
CNRS, Université de Toulouse, CNRS INP); Zlatan Stanojević, Oskar Baumgartner (Global
TCAD Solutions GmbH)
Session C2: Energy Harvesting/Voltage Converter
Chairman: Prof. Takahide Sato
C2.1 Electrical model and performance of an embedded MEMS energy harvester
Eduardo J. Holguin Weber∗ , Alexis Brenes, Lionel Trojman, Andrei Vladimirescu (Institut
supérieur d’électronique de Paris)
C2.2 Two stage boost converter with one inductor for energy harvesting
Kyogo Nakamurar∗ , Akira Hyogo, Ryo Kishida, Tatsuji Matsuura (Tokyo University of Science)
C2.3 Signal dynamic range expansion and power supply voltage reduction for an exponentiation
conversion IC
Naoya Nishiyama∗ , Fumiya Matsui, Yuji Sano (Toyo University)
C2.4 Transition response improvement of current sensing circuit using hysteresis comparator in buck-
boost converter for mobile devices
Yosuke Susa∗ , Ryo Kishida, Tatsuji Matsuura, Akira Hyogo (Tokyo University of Science)
C2.5 Undershoot reduction at load change by a capacitor connecting circuit in hysteretic DC-DC
buck converter
Kento Takayanagi∗ , Ryo Kishida, Tatsuji Matsuura, Akira Hyogo (Tokyo University of Science)
Note: ∗ is a presenter.
xiInternational Conference on Analog VLSI Circuits (AVIC 2021),
Bordeaux, France, 18th–21st Oct. 2021
Student Event
Thursday October 21st 9:00–12:00
Organized by IEEJ Research Committee of Cultivation Model of Electronics Engineer
Playing Actively on International Field
Observers: Prof. François Rivet, Prof. Kawori Sekine, Prof. Kazuyuki Wada, Dr. Toru Yazaki
This session is mainly for information exchange between local and international students and is or-
ganized by IEEJ research committee of cultivation model of electronics engineer playing actively on
international field. Participants are generally limited to students. Several quiz and group activities
with the themes related to electronics are being arranged. Please make use of this opportunity for
future research of young researchers through active communication and discussions.
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