RZ FAMILY MICROPROCESSORS - 64-Bit & 32-Bit High-performance MPUs - Renesas
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RZ FAMILY MICROPROCESSORS 64-Bit & 32-Bit High-performance MPUs 2023.04
THE NEXT-GENERATION PROCESSOR TO
MEET THE NEEDS OF THE SMART SOCIETY HAS ARRIVED.
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Control Network
CONTENTS
RZ/V SERIES_ ___________________________________________ 04
RZ/G SERIES____________________________________________ 08
RZ/A SERIES____________________________________________ 18
RZ/T SERIES_ ___________________________________________ 24
RZ/N SERIES____________________________________________ 35
PACKAGE LINEUP_ _______________________________________ 43
02-03
The utilization of intelligent technology is advancing in all aspects of our lives, including electric household appliances, industrial equipment, building
management, power grids, and transportation. The cloud-connected “smart society” is coming ever closer to realization. Microcontrollers are now expected
to provide powerful capabilities not available previously, such as high-performance and energy-efficient control combined with interoperation with IT
networks, support for human-machine interfaces, and more. To meet the demands of this new age, Renesas has drawn on its unmatched expertise in
microcontrollers to create the RZ family of embedded processors. The lineup of these “next-generation processors that are as easy to use as conventional
microcontrollers” to meet different customer requirements.
The Zenith of the Renesas micro
As embedded processors to help build the next generation of advanced products, the RZ family offers features not available elsewhere and brings new value
to customer applications.
RZ/V Series
64-bit Cortex®-A CPU, Up to 1.2GHz
Low-power Embedded AI
for Vision-AI Application
RZ/G Series
32/64-bit Cortex®-A CPU, Up to 1.5Hz
64-bit RISC-V CPU, Up to 1.0GHz
for HMI and IoT Application
RZ/A Series
32/64-bit Cortex®-A CPU, Up to 1GHz
- DDR3L/4 (RZ/A3UL)
- Up to 10MB Embedded RAM for HMI Application
RZ/T Series
32-bit Cortex®-R CPU, Up to 800MHz
Real-time Control
Multi-protocol Encoder I/F
for AC servo, Actuator, Inverter
RZ/N Series
32-bit Cortex®-A/M/R CPU, Up to 500MHz
Multi-protocol Industrial Network
for PLC, Remote IO, Gateway
Arm® and Cortex® are registered trademarks of Arm Limited (or its subsidiaries) in the EU and/or elsewhere.
RZ/V Series
RZ/V Series Roadmap
RZ/V-next (TBD)
RZ/V2M RZ/V2MA
Cortex®-A53 x2 (1GHz) Cortex®-A53x2 (1GHz)
DRP-AI, ISP
RZ/V2L DRP-AI, OpenCV Acc.
Cortex®-A55 x2 (1.2GHz)
Cotex®-M33 X1 (200MHz)
DRP-AI, Simple ISP
2019 2020 2021 2022 2023 2024 2025 2026 CY
RZ/V Series Features
AI Accelerator "DRP-AI" achieves high-speed AI inference and low power consumption
4K (2160p30) video codec and high-performance image signal processor (ISP) (RZ/V2M)
Provides Vision Processing Accelerator (OpenCV) and Image Signal Processor (Simple ISP) function as DRP library
Equipped with a 3D Graphics Engine for fast image rendering (RZ/V2L)
Adopts Civil Infrastructure Platform (CIP) Linux kernel that can be supported for more than 10 years
* DRP: Dynamically Reconfigurable Processor
Founded
in CY2016
RZ/V Series Application
IP Camera Surveillance camera Retail Logistics Image inspection
04-05
Features of DRP-AI
DRP-AI consists of AI-MAC (multiply-accumulate processor) and DRP (reconfigurable processor). AI processing can be executed at high speed by assigning AI-
MAC for operations on the convolution layer and fully connected layer, and DRP for other complex processing such as preprocessing and pooling layer.
For more detailed technical information on DRP-AI, please refer to the following white paper.
White Paper: Embedded AI-Accelerator DRP-AI
While most AI accelerators specialize only in AI inference and rely on the CPU for
pre- and post-processing, DRP-AI integrates pre- and post-processing and AI
inference into a single DRP-AI hardware to achieve superior AI processing
performance.
Use Case
Add-on the AI inference
Standalone system
on your system
Main System
Serial interface Result of AI
CSI, IIC, or UART
Capturing Output AI Capturing Output AI
image result image result
RZ/V RZ/V
MIPI or HDMI or MIPI or HDMI or
USB, etc. MIPI-DSI2 USB, etc. MIPI-DSI2
Ethernet Result of AI Ethernet Result of AI
or videos or videos
¢ RZ/V2M block diagram
RZ/V2M Group
System CPU Peripheral I/F
CPU Arm Debugger (CoreSight™) Arm® Cortex®-A53: 1GHz Arm® Cortex®-A53: 1GHz SDI (2ch)
2× Cortex-A53 (up to 1.0GHz) L1 I$: 32KB L1 D$: 32KB L1 I$: 32KB L1 D$: 32KB
DMAC (16ch) USB3.1 (1ch)
Vision and AI NEON FPU NEON FPU (Host/Peripheral)
AI Accelerator; DRP-AI at 1.0 TOPS/W class Power control
L2$: 512KB PCIe Gen2 (2Lane)
Image Signal Processor (ISP) of multi-stream available Timers
Camera Interface; 2× MIPI CSI-2 Gbit Ethernet MAC (1ch)
Timer (32ch) Memories
Face and Human Detection Engine I2C (4ch)
PWM (16ch) RAMA 200KB RAMB 1MB
Video and Graphics CSI (6ch)
H.265/H.264 Multi Codec WDT (2ch)
Sensing and Analyzing UART (2ch)
JPEG Codec Engine AI-accelerator (DRP-AI)
Image Sensor I/F GPIO
2D Graphics Engine MIPI CSI-2 v1.2 General Processing Multi-target detection Motor Controller
Display Interface (4Lanes, 2ch) Accelerator (Face, Person’s body)
MIPI-DSI (4-lane) Environment Sensor I/F
HDMI 1.4a Display I/F Video and Graphics
Camera ISP 2D Graphics engine External Memory I/F
Audio Interface HDMI v1.4a TX (1ch)
H.264/265 Multi Codec JPEG Codec LPDDR4 (32-bit)
Serial Sound Interface × 1ch
Audio I/F eMMC (1ch)
Communication Interface
SD Host × 2ch I2S (1ch) Security
Trusted Secure IP Analog
PCI-Express 2.0 (2-lane) × 1ch
ADC (20ch,12bit)
Gigabit Ethernet × 1ch
USB3.1 Gen1 Host/Function × 1ch Temperature sensor (2ch)
I2C Bus × 4ch
SCI × 6ch
UART × 2ch
Memory Interface
NAND Flash Interface ONFI1.0 × 1ch
eMMC 4.5.1 × 1ch
32-bit LPDDR4-3200 × 1ch
Security
Hardware Security Engine
¢ RZ/V2L block diagram
RZ/V2L Group
System CPU Peripheral I/F
CPU Arm Debugger (CoreSight™) Arm® Cortex®-A55: 1.2GHz Arm® Cortex®-A55: 1.2GHz Arm® SDHI (UHS-I, 1ch)
2× Cortex-A55 or 1× Cortex-A55 (up to 1.2GHz) DMAC (16ch) L1 I$: 32KB L1 D$: 32KB L1 I$: 32KB L1 D$: 32KB Cortex® USB2.0 (Host, 1ch)
1× Cortex-M33 (up to 200MHz) NEON FPU NEON FPU -M33
Power control 200MHz USB2.0 (Host/Peripheral, 1ch)
Vision and AI L3$: 256KB w/ECC Gbit Ethernet MAC (2ch)
AI Accelerator; DRP-AI Timers
I2C (4ch)
* Image Signal Processor (Simple ISP) Function is provided as DRP Library 32-bit Timer (1ch) Memories
RAM 128KB w/ECC SCI 8/9-bit (2ch)
Camera Interface; 1× MIPI CSI-2 / 1× Digital Parallel 16-bit Timer (8ch)
Video and Graphics SCIF(UART) (5ch)
PWM (8ch)
Sensing and Analyzing RSPI (3ch)
H.264 Codec WDT (3ch) AI-accelerator (DRP-AI)
3D Graphics Engine CAN-FD (2ch)
Display Interface Image Sensor I/F Video and Graphics GPIO
MIPI-DSI (4-lane) MIPI CSI-2 (4Lanes, 1ch) Image Scaling Unit (5M pixel) 3D GPU (Mali™-G31)
Parallel (HD-30fps, 1ch) External Memory I/F
Digital Parallel H.264 Enc/Dec (1920 × 1080pixel, 30fps)
DDR3L/DDR4-1600 (16-bit)
Audio Interface Display I/F
Serial Sound Interface × 4ch Security (option) SPI Multi I/O (8-bit DDR, 1ch)
MIPI DSI-2 (4Lanes, 1ch) Secure Boot Device Unique ID
Communication Interface SDHI (UHS-I) / eMMC (1ch)
Parallel (WXGA-60fps, 1ch) Crypto Engine JTAG Disable
Gigabit Ethernet × 2ch Analog
USB2.0 Host × 1ch Audio I/F TRNG OTP 4K-bit
12-bit ADC (8ch)
USB2.0 Host/Function × 1ch SSI (I2S, 4ch)
Thermal Sensor (1ch)
I2C Bus × 4ch SRC (1ch)
SCI × 2ch
UART × 5ch
Memory Interface
SPI Multi I/O (8bit DDR) × 1ch
SDHI (UHS-I) / eMMC × 1ch
16-bit DDR3L-1333/DDR4-1600 × 1ch
Security
Hardware Security Engine (Option)
06-07
¢ RZ/V2MA block diagram
RZ/V2MA Group
System CPU Peripheral I/F
CPU Arm Debugger (CoreSight™) Arm® Cortex®-A53: 1GHz Arm® Cortex®-A53: 1GHz SDI (2ch)
2× Cortex-A53 (up to 1.0GHz) L1 I$: 32KB L1 D$: 32KB L1 I$: 32KB L1 D$: 32KB
DMAC (16ch) USB3.1 (1ch)
Vision and AI NEON FPU NEON FPU (Host/Peripheral)
AI Accelerator; DRP-AI at 1.0 TOPS/W class Timers
L2$: 512KB PCle Gen2 (2Lane)
OpenCV Accelerator (DRP) Timer (32ch)
Video and Graphics Gbit Ethernet MAC (1ch)
PWM (16ch) Memories
H.265/H.264 Multi Codec IIC (4ch)
WDT (2ch) RAMA 200KB RAMB 1MB
Communication Interface CSI (6ch)
SD Host × 2ch Analog Sensing and Analyzing UART (2ch)
PCI-Express 2.0 (2-lane) × 1ch Temperature sensor (2ch) AI-accelerator (DRP-AI) Vision Accelerator (DRP) GPIO
Gigabit Ethernet × 1ch
USB3.1 Gen1 Host/Function × 1ch Video codec External Memory I/F
I2C Bus × 4ch H.264/265 Multi Codec LPDDR4 (32-bit)
SCI × 6ch eMMC (1ch)
UART × 2ch
Memory Interface
eMMC 4.5.1 × 1ch
32-bit LPDDR4-3200 × 1ch
Development Environment for AI
Renesas offers two development environments: DRP-AI Translator, designed to extract the full performance potential of DRP-AI, and DRP-AI
TVM,** which extends the coverage of the AI model to both DRP-AI and the CPU.
DRP-AI Translator
A translator that converts trained AI models in ONNX* format into object code for DRP-AI.
DRP-AI TVM**
This AI development environment brings the power of the Apache TVM open-source deep learning compiler to DRP-AI Translator and supports AI models
utilizing Arm processors as well as DRP-AI.
* ONNX: Open Neural Network Exchange
TM
** DRP-AI TVM is powered by EdgeCortix MERA Compiler Framework
RZ/G Series
RZ/G Series Roadmap
RZ/G2H
Cortex®-A57×4 (1.5GHz)
Cortex®-A53×4 (1.2GHz)
Cortex®-R7×1 (800MHz)
GX6650, H.264, H265
32bit×2ch LPDDR4-3200
RZ/G2M RZ/G-next
RZ/G1H Cortex®-A57×2 (1.5GHz)
Cortex®-A15x4 (1.4GHz) Cortex®-A53×4 (1.2GHz)
Cortex®-A7x4 (780MHz) Cortex®-R7×1 (800MHz)
G6400, H.264 GX6250, H.264, H265
32bit×2ch DDR3-1600 32bit×2ch LPDDR4-3200
RZ/G1M RZ/G2N
Cortex®-A15x2 (1.5GHz) Cortex®-A57×2 (1.5GHz)
SGX544MP2, H.264 Cortex®-R7×1 (800MHz)
32bit×2ch DDR3L-1600 GE7800, H.264, H.265
32bit×1ch LPDDR4-3200
RZ/G1N RZ/G2E
Cortex®-A15x2 (1.5GHz) Cortex®-A53×2 (1.2GHz)
SGX544MP2, H.264 Cortex®-R7×1 (800MHz)
32bit×1ch DDR3L-1600 GE8300, H.264,H.265
32bit×1ch DDR3L-1856
RZ/G1E RZ/G1C RZ/G2L
Cortex®-A55×1 or ×2 (1.2GHz)
Cortex®-A7x2 (1.0GHz) Cortex®-A7x2 (1.0GHz) Cortex®-M33×1 (200MHz)
SGX540, H.264 SGX531, H.264 Mali-G31, H.264
32bit×1ch DDR3-1333 32bit×1ch DDR3-1000 16bit×1ch DDR4/DDR3L
RZ/G2LC
Cortex®-A55×1 or ×2 (1.2GHz)
Cortex®-M33×1 (200MHz)
Mali-G31
16bit×1ch DDR4/DDR3L
RZ/G2UL
Cortex®-A55×1 (1.0GHz)
Cortex®-M33×1 (200MHz)
16bit×1ch DDR4/DDR3L
RZ/Five
AX45MP×1 (1.0GHz)
16bit DDR4/DDR3L
2016 2017 2018 2019 2020 2021 2022 2023 2024 CY
RZ/G2 Highlights
High Performance
64-bit Arm Cortex‑A cores, plus powerful 3D graphics engine and video engine capable of supporting up to 4K UHD, to offer the highest performance
Wide Coverage
Entry-level RZ/G2L Group 3 products equipped with Cortex-A55 with improved processing performance have been newly added to the RZ/G2 lineup
High Reliability
Built-in Error Correction Code (ECC) for internal and external memory, which is essential for high-reliability mission critical systems
Super Long Term Support (SLTS)
Applying Civil Infrastructure Platform (CIP) Linux, the Linux kernel will be provided with over 10 years of maintenance
Verified Linux Package
Renesas verifies and provides a Linux package that combines CIP and Linux basic software. Minimize your Linux maintenance resources
RZ/G2 Specification 1
Items RZ/G2H RZ/G2M RZ/G2N RZ/G2E
CPU 4× Cortex®-A57@1.5GHz 2× Cortex®-A57@1.5GHz 2× Cortex®-A57@1.5GHz 2× Cortex®-A53@1.2GHz
(Arm® Cortex®-A) 4× Cortex®-A53@1.2GHz 4× Cortex®-A53@1.2GHz L1,L2 Parity/ECC L1,L2 Parity/ECC
L1,L2 Parity/ECC L1,L2 Parity/ECC
CPU 1× Cortex®-R7@800MHz 1× Cortex®-R7@800MHz 1× Cortex®-R7@800MHz 1× Cortex®-R7@800MHz
(Arm® Cortex®-R) L1,TCM w/ECC L1,TCM w/ECC L1,TCM w/ECC L1,TCM w/ECC
DRAM I/F 32-bit ×2ch LPDDR4(3200) w/ECC 32-bit ×2ch LPDDR4(3200) w/ECC 32-bit ×1ch LPDDR4(3200) w/ECC 32-bit ×1ch DDR3L(1856) w/ECC
Video in 2×MIPI-CSI2, 2×Digital (RGB/YCbCr) 2×MIPI-CSI2, 2×Digital (RGB/YCbCr) 2×MIPI-CSI2, 2×Digital (RGB/YCbCr) 1×MIPI-CSI2, 1×Digital(RGB/YCbCr)
up to 8 input image can be captured up to 8 input image can be captured up to 8 input image can be captured up to 2 input image can be captured
Video Codec Support up to 4k resolutions Decoding: H.265, Support up to 4k resolutions Decoding: H.265, Support up to 4k resolutions Decoding: H.265, Support up to FHD resolutions Decoding: H.265,
Encoding and Decoding: H.264 Encoding and Decoding: H.264 Encoding and Decoding: H.264 Encoding and Decoding: H.264
3D GFX PowerVR GX6650@600MHz PowerVR GX6250@600MHz PowerVR GE7800@600MHz PowerVR GE8300@600MHz
Display out 1×HDMI, 1×LVDS, 1×Digital RGB 1×HDMI, 1×LVDS, 1×Digital RGB 1×HDMI, 1×LVDS, 1×Digital RGB 2×LVDS or 1×LVDS, 1×Digital RGB
USB USB2.0×2ch (1H, 1H/F/OTG) USB2.0×2ch (1H, 1H/F/OTG) USB2.0×2ch (1H, 1H/F/OTG) USB2.0×1ch (H/F)
USB3.0/2.0×1ch (DRD) USB3.0/2.0×1ch (DRD) USB3.0/2.0×1ch (DRD) USB3.0/2.0×1ch (DRD)
Gbit Ether 1ch 1ch 1ch 1ch
CAN 2ch (support CAN-FD) 2ch (support CAN-FD) 2ch (support CAN-FD) 2ch (support CAN-FD)
PCIe 2ch (Rev2.0 1Lane) 2ch (Rev2.0 1Lane) 2ch (Rev2.0 1Lane) 1ch (Rev2.0 1Lane)
one of the 2ch is shared with SATA one of the 2ch is shared with SATA
SATA 1ch (Pin Shared) No 1ch (Pin Shared) No
Package 1022pin FCBGA, 29mm×29mm 1022pin FCBGA, 29mm×29mm 1022pin FCBGA, 29mm×29mm 552pin FCBGA, 21mm×21mm
0.8mm ball pitch 0.8mm ball pitch 0.8mm ball pitch 0.8mm ball pitch
Pin Compatible
08-09
RZ/G2 Specification 2
RZ/G2UL (Type2) RZ/G2UL (Type1)
Items RZ/G2L RZ/G2LC
Pin compatible with RZ/G2LC Full function
CPU 1× or 2× Cortex®-A55@1.2GHz 1× or 2× Cortex®-A55@1.2GHz 1× Cortex®-A55@1.0GHz 1× Cortex®-A55@1.0GHz
(Arm® Cortex®-A) L1,L3 Parity/ECC L1,L3 Parity/ECC L1,L3 Parity/ECC L1,L3 Parity/ECC
CPU 1× Cortex®-M33@200MHz 1× Cortex®-M33@200MHz 1× Cortex®-M33@200MHz 1× Cortex®-M33@200MHz
(Arm® Cortex®-M)
DRAM I/F 16-bit ×1ch DDR4-1600/DDR3L-1333 w/ECC 16-bit ×1ch DDR4-1600/DDR3L-1333 w/ECC 16-bit ×1ch DDR4-1600/DDR3L-1333 w/ECC 16-bit ×1ch DDR4-1600/DDR3L-1333 w/ECC
Video in 1×MIPI CSI-2 or 1×Digital Parallel input 1×MIPI CSI-2 1×MIPI CSI-2 1×MIPI CSI-2
Video Codec Support up to Full HD @30fps resolutions – – –
Encoding and Decoding: H.264
3D GFX Arm Mali-G31 GPU @500MHz Arm Mali-G31 GPU @500MHz – –
Display out 1×MIPI DSI or 1×Digital Parallel output 1×MIPI DSI – 1×Digital Parallel output
USB USB2.0×2ch (1Host, 1Host/Function/OTG) USB2.0×2ch (1Host, 1Host/Function/OTG) USB2.0×2ch (1Host, 1Host/Function/OTG) USB2.0×2ch (1Host, 1Host/Function/OTG)
Gbit Ether 2ch 1ch 1ch 2ch
CAN 2ch (support CAN-FD) 2ch (support CAN-FD) 2ch (support CAN-FD) 2ch (support CAN-FD)
12-bit ADC 8ch – – 2ch
Package 551pin LFBGA, 21mm×21mm 361pin LFBGA, 13mm×13mm 361pin LFBGA, 13mm×13mm 361pin LFBGA, 13mm×13mm
0.8mm ball pitch 0.5mm ball pitch 0.5mm ball pitch 0.5mm ball pitch
456pin LFBGA, 15mm×15mm
0.5mm ball pitch
Pin Compatible
RZ/Five (RISC-V) Features and Specification
The RZ/Five is an entry-class general-purpose Linux MPU with a Items RZ/Five
64-bit RISC-V architecture. CPU 64bit RISC-V CPU Core
General-purpose MPU adopting an Open Instruction Set AndesCore™ AX45MP Single core 1.0 GHz
Architecture RISC-V DRAMI/F 16-bit × 1ch DDR4-1600/DDR3L-1333 w/ECC
Provide development environment to easy mutual migration USB USB2.0 × 2ch (1Host, 1Host/Function/OTG)
between ARM and RISC-V Gbit Ether 2ch : 13mm × 13mm Package
General-purpose MPU specialized for IoT Edge 1ch : 11mm × 11mm Package
CAN 2ch (support CAN-FD)
12-bit ADC 2ch
Package 361pin, LFBGA, 13mm × 13mm, 0.5mm pitch
266pin, LFBGA, 11mm × 11mm, 0.5mm pitch
Super Long Term Software Support
Renesas RZ/G and RZ/V microprocessors are the only embedded MPUs that meet the long-term support demands for industrial and
infrastructure equipment manufacturers through the 10+ year support offered by the Super Long Term Support (SLTS) kernel maintained by the
Civil Infrastructure Platform (CIP). The CIP SLTS Linux kernel supports countermeasures against vulnerability to security attacks with a long-
term maintenance period of 10 years or more. This reduces Linux maintenance costs and simplifies adoption of reliable industrial-grade Linux.
Verified Linux Package(VLP) Reduces Cost and Simplifies Design
The “Verified Linux Package (VLP)” for the RZ/G and RZ/V series is a combination of the Civil Infrastructure Platform (CIP) Core Package and the
basic software (Linux BSP, multimedia, graphics, security, etc.) for IoT devices. This packaged software is verified by Renesas and is available
from the Renesas RZ Linux platform site. With VLPs, you can start developing applications quickly while minimizing Linux maintenance
resources.
GUI Framework
Verified Linux Package Qt application framework
HTML5 application framework
GUI Framework
Video Codec OpenGL Security
(Qt/HTML5)
Multimedia
User land
Renesas
H.264 Codec
Open Source Software H.265 Decoder
3D graphics
Linux Library Gstreamer Window system
Secure Middle Ware
Encrypted kernel boot
Security communication
CIP Core package Secure storage
Kernel space
Linux Kernel CIP SLTS Kernel
Civil Infrastructure Platform project
CIP
RZ/G Device Drivers On-board 10+ years super long term support
CIP kernel
RZ/V Device Drivers Device Drivers Reliability/Security/Real-time
RZ/G*1, RZ/V Reference Board
*1: RZ/G Reference Board is used for Kernel development as a software development platform for CIP projects.10-11
Flexible Development Kits
RZ/G2 development kits support the industry standard 96Boards specification and SMARC specification to enable evaluation and speed
development with wide variety of mezzanine boards and existing carrier boards. Renesas provides circuit schematics, component BOMs, and
board layout data to make it easy to spin your own custom hardware.
¢ RZ/G2H,G2M,G2N Development Kit (96Boards format compatible) ¢ RZ/G2E Development Kit (96Boards format compatible)
Main Memory: 4 GB DDR4 Main Memory: 2 GB DDR3L
QSPI NOR FLASH 64 MByte QSPI NOR FLASH 64 MByte
2
I C EEPROM 512 Byte I2C EEPROM 512 Byte
External Storage: micro SD × 1 External Storage: micro SD × 1
Connectivity: USB 2.0 × 2ch, Connectivity: USB 2.0 × 2ch,
USB 3.0 × 1ch, GbE × 1 USB 3.0 × 1ch, GbE × 1
HDMI out / LVDS out or MIPI DSI out HDMI out / LVDS out or MIPI DSI out
Wi-Fi + BT Wi-Fi + BT
¢ RZ SMARC v2.1 Module + Carrier Board
RZ/G2L, RZ/G2LC, RZ/G2UL SMARC Module
– Size: 82mm × 50mm
– Processor: RZ/G2L, RZ/G2LC, RZ/G2UL (Type-1)
– Main Memory: 2GB DDR4 (1GB × 2) *G2UL: 1GB (1GB × 1)
– QSPI NOR FLASH: 16MB
– eMMC Memory: 64GB
– External Storage: micro SD × 1
– A/D Converter Interface × 2
– JTAG connector
RZ/Five SMARC Module
– Size: 82mm × 50mm
– Processor: RZ/Five
– Main Memory: 1GB DDR4 (1GB × 1)
– QSPI NOR FLASH: 16MB
– eMMC Memory: 64GB
– External Storage: micro SD × 1
– A/D Converter Interface × 2
– JTAG connector
Carrier Board
– Size: 160mm × 100mm – External Storage: micro SD × 1
– Gigabit Ethernet × 2 – Audio Line In × 1
– USB2.0 × 2ch (OTG × 1ch, Host × 1ch) – Audio Line Out × 1
– MIPI CSI-2 Camera connector (can connect to Google Coral Camera) – PMOD × 2
– Micro HDMI (output) connector – USB-Type C for Power Input
– CAN-FD × 2HMI Solutions
RZ/G Series
Max • WXGAto 4K, functions: 3D Graphics, Video Codec
Display • OS: Linux (RichOS)
resolution Generation2 (64-bit CPU)
4K
(3840 × 2160)
RZ/G2H
RZ/G2M
Generation1 (32-bit CPU) RZ/G2N
RZ/G1H RZ/G2E
RZ/G1M
New
Full HD
(1920 × 1080) RZ/G1N Generation2 (64-bit CPU)
RZ/G1E RZ/G2L
RZ/G1C RZ/G2LC
RZ/G2UL
WXGA and below RZ/A
(1280 × 768)
Series
RTOS 32-bit Linux 64-bit Linux Operating
System
RZ/G2H (R8A774Ex)
CPU core Video codec module: VCP4 × 1 ¢ RZ/G2H (R8A774Ex) block diagram
Arm® Cortex®-A57, quad-core channel
Max. operating frequency: 1.5GHz IP converter module System CPU Connectivity
Arm® Cortex®-A53, quad-core Video image processing functions System controller 4 × Cortex®-A57 1.5GHz 4 × Cortex®-A53 1.2GHz 1 × Cortex®-R7 800MHz 2 × PCIe2.0 (1Lane)
Max. operating frequency: 1.2GHz (color conversion, image enlarge- System RAM: 384KB L1 I$ 48KB L1 I$ 32KB L1 I$ 32KB SATA (Rev.3.2) (shared)
Arm® Cortex®-R7, single-core L1 D$ 32KB L1 D$ 32KB L1 D$ 32KB
ment/reduction, filtering) Thermal Sensor USB3.0/2.0 (DRD)
NEON/VFPv4 NEON/VFPv4 VFPv3-D16
Max. operating frequency: 800MHz Audio functions JTAG Debug 4 × USB2.0 (2H, 2H/F/OTG)
Cache memory (Cortex®-A57) Sampling rate converter × 10 (CoreSight™) L2 cache: 2MB with ECC L2 cache: 512KB with ECC I-TCM 32KB, D-TCM 32KB
with ECC Ethernet AVB (1Gbps)
L1 instruction cache: 48KB channels Timers 3D Graphics 2 × CAN2.0B / 2 × CAN-FD
L1 data cache: 32KB Serial sound interface × 10 channels 26 × 32-bit Timer PowerVR GX6650 6 × UART, 5 × H-UART
L2 cache: 2MB Storage interfaces 15 × 32-bit Interval 2D/3D tile based 600MHz 4 × SPI
Cache memory (Cortex®-A53) USB 3.0 DRD × 1 channel 7 × I2C; 1 × DVFS ctrl
WDT Video Codec
L1 instruction cache: 32KB USB 2.0 × 2 channels (Host only 1 Memory I/F
7 × PWM out Up to 4K resolution
L1 data cache: 32KB channel/Host-Function 1channel) (2 channels) 32-bit × 2ch LPDDR4-3200
L2 cache: 512KB SD host interface × 4 channels Audio IPs (ECC)
Cache memory (Cortex®-R7) Multimedia card interface × 2 Audio router w/10 ASRC, Video IP access cache
L1 instruction cache: 32KB channels mixer, 10 I2S (6ch TDM), 3 × Display out 4 × Video Signal Processor 16-bit ExtBus/SRAM
90ch Audio DMA 1 × Digital out, 1 × LVDS
L1 data cache: 32KB Serial ATA interface × 1 channel 1 × HDMI 2 × Fine Display Processor 1 × QSPI (4/8-bit selectable)
I-TCM: 32KB or 1 × Hyperflash
Other peripheral functions Secure IP 8 × Video in
2 × MIPI-CSI2 4 × SDIO (SDR104)
D-TCM: 32KB 32-bit timer × 15 channels Crypto engine (1 × 4L, 1 × 2L)
External memory PWM timer × 7 channels (AES, DES, Hash, RSA, TRNG) 2 × Digital 2 × eMMC (5.0, HS400)
Ability to connect LPDDR4-SDRAM I2C bus interface × 7 channels FC-BGA: 29 × 29mm2 1022-pins, 0.8mm pitch
via DDR dedicated bus Serial communication interface (SCIF)
Data bus width: 32 bits × 2 channels × 6 channels
External expansion Quad serial peripheral interface (QSPI)
Ability to connect flash ROM or SRAM × 2 channels (boot support)
directly Clock-synchronous serial interface
Data bus width: 8/16 bits (MSIOF) × 4 channels (SPI/IIS
PCI Express 2.0 : 1 Lane × 2 channels support)
(one of PHY is shared with Serial ATA) Ethernet controller with AVB support
3D graphics (support for IEEE 802.1BA, IEEE
PowerVR™ GX6650 802.1AS, IEEE 802.1Qav, and IEEE
Video functions 1722)
Video display interface × 3 channels (1 Controller area network (CAN)
channel: HDMI(option), 1 channel: interface × 2 channels
LVDS, 1 channel: RGB888) Interrupt controller (INTC)
Video input interface × 4 channels (2 Clock generator (CPG): on-chip PLL
channels: MIPI-CSI2, 2 channels: On-chip debug function
Digital(RGB/YCbCr))12-13
RZ/G2M (R8A774Ax)
CPU core Video codec module: VCP4 × 1 channel ¢ RZ/G2M (R8A774Ax) block diagram
Arm® Cortex®-A57, quad-core IP converter module
Max. operating frequency: 1.5GHz Video image processing functions (color System CPU Connectivity
Arm® Cortex®-A53, quad-core conversion, image enlargement/ System controller 2 × Cortex®-A57 1.5GHz 4 × Cortex®-A53 1.2GHz 1 × Cortex®-R7 800MHz 2 × PCIe2.0 (1Lane)
Max. operating frequency: 1.2GHz reduction, filtering) System RAM: 384KB L1 I$ 48KB L1 I$ 32KB L1 I$ 32KB
Arm® Cortex®-R7, single-core Audio functions Thermal Sensor L1 D$ 32KB L1 D$ 32KB L1 D$ 32KB USB3.0/2.0 (DRD)
NEON/VFPv4 NEON/VFPv4 VFPv3-D16
Max. operating frequency: 800MHz Sampling rate converter × 10 channels JTAG Debug 2 × USB2.0 (1H, 1H/F/OTG)
Cache memory (Cortex®-A57) Serial sound interface × 10 channels (CoreSight™) L2 cache: 2MB with ECC L2 cache: 512KB with ECC I-TCM 32KB, D-TCM 32KB
with ECC Ethernet AVB (1Gbps)
L1 instruction cache: 48KB Storage interfaces Timers 3D Graphics 2 × CAN2.0B / 2 × CAN-FD
L1 data cache: 32KB USB 3.0 DRD × 1 channel 26 × 32-bit Timer PowerVR GX6250 6 × UART, 5 × H-UART
L2 cache: 2MB USB 2.0 × 2 channels (Host only 1 15 × 32-bit Interval 2D/3D tile based 600MHz 4 × SPI
Cache memory (Cortex®-A53) channel/Host-Function 1channel) 7 × I2C; 1 × DVFS ctrl
WDT Video Codec
L1 instruction cache: 32KB SD host interface × 4 channels Memory I/F
7 × PWM out Up to 4K resolution
L1 data cache: 32KB Multimedia card interface × 2 channels 32-bit × 2ch LPDDR4-3200
(2 channels)
L2 cache: 512KB Other peripheral functions Audio IPs (ECC)
Cache memory (Cortex®-R7) 32-bit timer × 15 channels Audio router w/10 ASRC, Video IP access cache
L1 instruction cache: 32KB PWM timer × 7 channels mixer, 10 I2S (6ch TDM), 3 × Display Out 4 × Video Signal Processor Raw NAND
90ch Audio DMA 1 × Digital out, 1 × LVDS (8/16-bit, ONFI 1.x,
L1 data cache: 32KB I2C bus interface × 7 channels 1 × HDMI 2 × Fine Display Processor
ECC 1-8-bits)
I-TCM: 32KB Serial communication interface (SCIF) × Secure IP 8 × Video in
2 × MIPI-CSI2 16-bit ExtBus/SRAM
D-TCM: 32KB 6 channels Crypto engine (1 × 4L, 1 × 2L) 1 × QSPI (4/8-bit selectable)
External memory Quad serial peripheral interface (QSPI) (AES, DES, Hash, RSA, TRNG) 2 × Digital
or 1 × Hyperflash
Ability to connect LPDDR4-SDRAM via × 2 channels (boot support) FC-BGA: 29 × 29mm2 1022-pins, 0.8mm pitch
4 × SDIO (SDR104)
DDR dedicated bus Clock-synchronous serial interface
2 × eMMC (5.0, HS400)
Data bus width: 32 bits × 2 channels (MSIOF) × 4 channels (SPI/IIS support)
External expansion Ethernet controller with AVB support
Ability to connect flash ROM or SRAM (support for IEEE 802.1BA, IEEE 802.1AS,
directly IEEE 802.1Qav, and IEEE 1722, GMII/MII
Data bus width: 8/16 bits interface, PHY device connection
PCI Express 2.0 : 1 Lane × 2 channels support)
(one of PHY is shared with Serial ATA) Ethernet controller with AVB support
3D graphics (support for IEEE 802.1BA, IEEE 802.1AS,
PowerVR™ GX6250 IEEE 802.1Qav, and IEEE 1722)
Video functions Controller area network (CAN) interface
Video display interface × 3 channels (1 × 2 channels
channel: HDMI(option), 1 channel: LVDS, Interrupt controller (INTC)
1 channel: RGB888) Clock generator (CPG): on-chip PLL
Video input interface × 4 channels (2 On-chip debug function
channels: MIPI-CSI2, 2 channels:
Digital(RGB/YCbCr))
RZ/G2N (R8A774Bx)
CPU core Video codec module: VCP4 × 1 channel ¢ RZ/G2N (R8A774Bx) block diagram
Arm® Cortex®-A57, quad-core IP converter module
Max. operating frequency: 1.5GHz Video image processing functions (color System CPU Connectivity
Arm® Cortex®-R7, single-core conversion, image enlargement/ System controller 2 × Cortex®-A57 1.5GHz 1 × Cortex®-R7 800MHz 2 × PCIe2.0 (1Lane)
Max. operating frequency: 800MHz reduction, filtering) System RAM: 384KB L1 I$ 48KB L1 I$ 32KB SATA (Rev.3.2) (shared)
Cache memory (Cortex®-A57) Audio functions Thermal Sensor L1 D$ 32KB L1 D$ 32KB USB3.0/2.0 (DRD)
NEON/VFPv4 VFPv3-D16
L1 instruction cache: 48KB Sampling rate converter × 10 channels JTAG Debug 2 × USB2.0 (1H, 1H/F/OTG)
L1 data cache: 32KB Serial sound interface × 10 channels (CoreSight™) L2 cache: 1MB with ECC I-TCM 32KB, D-TCM 32KB with ECC Ethernet AVB (1Gbps)
L2 cache: 2MB Storage interfaces Timers 3D Graphics 2 × CAN2.0B / 2 × CAN-FD
Cache memory (Cortex®-R7) USB 3.0 DRD × 1 channel 26 × 32-bit Timer PowerVR GE7800 6 × UART, 5 × H-UART
L1 instruction cache: 32KB USB 2.0 × 2 channels (Host only 1 15 × 32-bit Interval 2D/3D tile based 600MHz 4 × SPI
L1 data cache: 32KB channel/Host-Function 1channel) 7 × I2C; 1 × DVFS ctrl
WDT Video Codec
I-TCM: 32KB SD host interface × 4 channels Memory I/F
7 × PWM out Up to 4K resolution
D-TCM: 32KB Multimedia card interface × 2 channels 32-bit × 1ch LPDDR4-3200
(2 channels)
External memory Serial ATA interface × 1 channel Audio IPs (ECC)
Ability to connect LPDDR4-SDRAM via Other peripheral functions Audio router w/10 ASRC, Video IP access cache
DDR dedicated bus 32-bit timer × 15 channels mixer, 10 I2S (6ch TDM), 3 × Display out 2 × Video Signal Processor Raw NAND
90ch Audio DMA 1 × Digital out, 1 × LVDS (8/16-bit, ONFI 1.x,
Data bus width: 32 bits × 1 channel PWM timer × 7 channels 1 × HDMI 1 × Fine Display Processor
ECC 1-8-bits)
External expansion I2C bus interface × 7 channels Secure IP 8 × Video in
2 × MIPI-CSI2 16-bit ExtBus/SRAM
Ability to connect flash ROM or SRAM Serial communication interface (SCIF) × Crypto engine (1 × 4L, 1 × 2L) 1 × QSPI (4/8-bit selectable)
directly 6 channels (AES, DES, Hash, RSA, TRNG) 2 × Digital
or 1 × Hyperflash
Data bus width: 8/16 bits Quad serial peripheral interface (QSPI) FC-BGA: 29 × 29mm2 1022-pins, 0.8mm pitch
4 × SDIO (SDR104)
PCI Express 2.0 : 1 Lane × 2 channels × 2 channels (boot support)
2 × eMMC (5.0, HS400)
(one of PHY is shared with Serial ATA) Clock-synchronous serial interface
3D graphics (MSIOF) × 4 channels (SPI/IIS support)
PowerVR™ GE7800 Ethernet controller with AVB support
Video functions (support for IEEE 802.1BA, IEEE 802.1AS,
Video display interface × 3 channels (1 IEEE 802.1Qav, and IEEE 1722)
channel: HDMI(option), 1 channel: LVDS, Controller area network (CAN) interface
1 channel: RGB888) × 2 channels
Video input interface × 4 channels (2 Interrupt controller (INTC)
channels: MIPI-CSI2, 2 channels: Clock generator (CPG): on-chip PLL
Digital(RGB/YCbCr)) On-chip debug functionRZ/G2E (R8A774C0)
CPU core Video codec module: VCP4 × 1 channel ¢ RZ/G2E (R8A774C0) block diagram
Arm® Cortex®-A53, quad-core IP converter module
Max. operating frequency: 1.2GHz Video image processing functions (color System CPU Connectivity
Arm® Cortex®-R7, single-core conversion, image enlargement/ System controller 2 × Cortex®-A53 1.2GHz 1 × Cortex®-R7 800MHz 1 × PCIe2.0 (1Lane)
Max. operating frequency: 800MHz reduction, filtering) System RAM: 128KB L1 I$ 32KB L1 I$ 32KB
Cache memory (Cortex®-A53) Audio functions Thermal Sensor L1 D$ 32KB L1 D$ 32KB USB3.0/2.0 (DRD)
NEON/VFPv4 VFPv3-D16
L1 instruction cache: 32KB Sampling rate converter × 10 channels JTAG Debug USB2.0 (1H/F)
L1 data cache: 32KB Serial sound interface × 10 channels (CoreSight™) L2 cache: 256KB with ECC I-TCM 32KB, D-TCM 32KB with ECC Ethernet AVB (1Gbps)
L2 cache: 256KB Storage interfaces Timers 3D Graphics 2 × CAN2.0B / 2 × CAN-FD
Cache memory (Cortex®-R7) USB 3.0 DRD × 1 channel 26 × 32-bit Timer PowerVR GE8300 6 × UART, 5 × H-UART
L1 instruction cache: 32KB USB 2.0 × 1 channel (Host-Function 15 × 32-bit Interval 2D/3D tile based 600MHz 4 × SPI
L1 data cache: 32KB 1channel) 8 × I2C; 1 × DVFS ctrl
WDT Video Codec
I-TCM: 32KB SD host interface × 3 channels Memory I/F
7 × PWM out
D-TCM: 32KB Multimedia card interface × 1 channel Up to FHD resolution
32-bit DDR3L-1856
External memory Other peripheral functions Audio IPs (ECC)
Ability to connect DDR3L-SDRAM via 32-bit timer × 15 channels Audio router w/10 ASRC, Video IP access cache
DDR dedicated bus PWM timer × 7 channels mixer, 10 I2S (6ch TDM), 2 × Display out: 2 × Video Signal Processor Raw NAND
45ch Audio DMA (2 × LVDS or (8-bit, ONFI 1.x,
Data bus width: 32 bits × 1channel I2C bus interface × 8 channels 1 × LVDS + 1 × DRGB)
1 × Fine Display Processor
ECC 1-8-bits)
External expansion Serial communication interface (SCIF) × Secure IP 2 × Video in 16-bit ExtBus/SRAM
Ability to connect flash ROM or SRAM 6 channels Crypto engine 1 × MIPI-CSI2 (1 × 2L)
1 × Digital 1 × QSPI (4/8-bit selectable)
directly Quad serial peripheral interface (QSPI) (AES, DES, Hash, RSA, TRNG)
or 1 × Hyperflash
Data bus width: 8/16 bits × 2 channels (boot support) FC-BGA: 21 × 21mm2 552-pins, 0.8mm pitch
3 × SDIO (SDR104)
PCI Express 2.0 : 1 Lane × 1 channel Clock-synchronous serial interface
eMMC (5.0, HS400)
3D graphics (MSIOF) × 4 channels (SPI/IIS support)
PowerVR™ GE8300 Ethernet controller with AVB support
Video functions (support for IEEE 802.1BA, IEEE 802.1AS,
Video display interface × 2 channels (2 IEEE 802.1Qav, and IEEE 1722)
channels: LVDS, 1 channel: RGB888) Controller area network (CAN) interface
Video input interface × 3 channels (1 × 2 channels
channels: MIPI-CSI2, 2 channels: Interrupt controller (INTC)
Digital(RGB/YCbCr)) Clock generator (CPG): on-chip PLL
On-chip debug function
RZ/G2L(R9A07G044Lxx)
CPU core Audio functions ¢ RZ/G2L(R9A07G044Lxx) block diagram
Arm® Cortex®-A55, dual-core or Sampling rate converter × 1 channel
single-core Serial sound interface × 4 channels System CPU Interfaces
Max. operating frequency: 1.2GHz Storage interfaces Arm Debugger Cortex®-A55 1.2GHz Cortex®-A55(#) 1.2GHz DDR4/DDR3L (In line ECC)
Arm® Cortex®-M33, single-core USB 2.0 × 2 channels (Host only 1 (CoreSight™) NEON/VFP NEON/VFP 16-bit × 1.6/1.3Gbps
Max. operating frequency: 200MHz channel/Host-Function 1channel) Arm TrustZone I-L1$: 32KB w/Parity I-L1$: 32KB w/Parity 1 × SPI Multi I/O
16ch DMAC D-L1$: 32KB w/ECC D-L1$: 32KB w/ECC (8-bit DDR)
Cache memory (Cortex®-A55) SD host interface × 2 channels Cortex®-M33
Interrupt Controller L2$: 0KB L2$: 0KB 2 × SDHI (UHS-I)/MMC
L1 instruction cache: 32KB Multimedia card interface × 1 channel @200MHz
L1 data cache: 32KB (Shared with SDHI) PLL/SSCG L3$(Shared) : 256KB w/ECC
1 × USB2.0 Host
L3 cache: 256KB Other peripheral functions Standby Memory 1 × USB2.0
External memory 32-bit timer × 1 channel (Sleep/Software/Module) Host / Function
RAM 128KB w/ECC
Ability to connect DDR4-SDRAM / 16-bit timer × 8 channels Timers 2 × 100/1000Mbps
DDR3L-SDRAM via DDR dedicated bus PWM timer × 8 channels Video & Graphics Ether MAC*
1 × 32-bit MTU3*
Data bus width: 16 bits × 1 channel I2C bus interface × 4 channels 3D GPU Camera In
8 × 16-bit MTU3* (MIPI CSI-2 4lane, Parallel*) 2 × I2C, 2 × I2C*
Arm Mali-G31
3D graphics Serial communication interface with 8 × 32-bit PWM* 2 × SCI 8/9-bit*
Display Out
Arm Mali™-G31 GPU FIFO (SCIF) × 5 channels (MIPI DSI 4lane, Parallel*)
3 × WDT* H.264 Enc/Dec 5 × SCIF (UART)*
Video functions Serial communication interface (SCI) × 1920 × 1080 @30fps Image Scaling Unit 3 × RSPI*
Video display interface: 2 channels Analog
2 × CAN-FD*
MIPI DSI × 1 channel or Digital parallel SPI Multi I/O Bus Controller× 1 channel 8 × 12-bit ADC Security (option)
Secure Boot Device Unique ID GPIO*
output × 1 channel (8bit Double data rate)
Video input interface: Serial Peripheral Interface (RSPI) × Crypto Engine JTAG Disable Audio
MIPI CSI-2 × 1 channel or Digital 3channels TRNG OTP 4Kbit 4 × SSI (I2S)*
parallel input × 1 channel Gigabit Ethernet controller × 2 channels (#) Single Core version is 1CPU. 1 × SRC
Video codec module: VCPL4 × 1 channel Controller area network (CAN) interface *Shared
Video image processing functions × 2 channels (support CAN FD)
(Resizer and Color Space / Color Format 12-bit A/D converter × 8 channels
Conversion) Interrupt controller
Clock generator (CPG): on-chip PLL
On-chip debug function14-15
RZ/G2LC(R9A07G044Cxx)
CPU core Audio functions ¢ RZ/G2LC(R9A07G044Cxx) block diagram
Arm® Cortex®-A55, dual-core or Sampling rate converter × 1 channel
single-core Serial sound interface × 2 channels System CPU Interfaces
Max. operating frequency: 1.2GHz Storage interfaces Arm Debugger Cortex®-A55 1.2GHz Cortex®-A55(#) 1.2GHz DDR4/DDR3L (In line ECC)
Arm® Cortex®-M33, single-core USB 2.0 × 2 channels (Host only 1 (CoreSight™) NEON/VFP NEON/VFP 16-bit × 1.6/1.3Gbps
Max. operating frequency: 200MHz channel/Host-Function 1channel) Arm TrustZone I-L1$: 32KB w/Parity I-L1$: 32KB w/Parity 1 × SPI Multi I/O
16ch DMAC D-L1$: 32KB w/ECC D-L1$: 32KB w/ECC (4-bit DDR)
Cache memory (Cortex®-A55) SD host interface × 2 channels Cortex®-M33
Interrupt Controller L2$: 0KB L2$: 0KB 2 × SDHI (UHS-I)/MMC
L1 instruction cache: 32KB Multimedia card interface × 1 channel @200MHz
L1 data cache: 32KB (Shared with SDHI) PLL/SSCG L3$(Shared) : 256KB w/ECC
1 × USB2.0 Host
L3 cache: 256KB Other peripheral functions Standby Memory 1 × USB2.0
External memory 32-bit timer × 1 channel (Sleep/Software/Module) Host / Function
RAM 128KB w/ECC
Ability to connect DDR4-SDRAM / 16-bit timer × 5 channels Timers 1 × 100/1000Mbps
DDR3L-SDRAM via DDR dedicated bus PWM timer × 4 channels Video & Graphics Ether MAC*
1 × 32-bit MTU3*
Data bus width: 16 bits × 1 channel I2C bus interface × 4 channels 3D GPU Camera In
5 × 16-bit MTU3* (MIPI CSI-2 4lane) 2 × I2C, 2 × I2C*
Arm Mali-G31
3D graphics Serial communication interface with 4 × 32-bit PWM* 2 × SCI 8/9-bit*
Display Out
Arm Mali™-G31 GPU FIFO (SCIF) × 3 channels Image Scaling Unit (MIPI DSI 4lane)
3 × WDT* 3 × SCIF (UART)*
Video functions Serial communication interface (SCI) ×
3 × RSPI*
Video display interface: 2 channels
2 × CAN-FD*
MIPI DSI × 1 channel SPI Multi I/O Bus Controller× 1 channel Security (option)
Video input interface: Secure Boot Device Unique ID GPIO*
(4bit Double data rate)
MIPI CSI-2 × 1 channel Serial Peripheral Interface (RSPI) × Crypto Engine JTAG Disable Audio
Video image processing functions 3channels TRNG OTP 4Kbit 2 × SSI (I2S)*
(Resizer and Color Space / Color Format Gigabit Ethernet controller × 1 channel (#) Single Core version is 1CPU. 1 × SRC
Conversion) Controller area network (CAN) interface *Shared
× 2 channels (support CAN FD)
Interrupt controller
Clock generator (CPG): on-chip PLL
On-chip debug function
RZ/G2UL(R9A07G043Uxx)
CPU core Audio functions ¢ RZ/G2UL(R9A07G043Uxx) block diagram
Arm® Cortex®-A55, single-core Sampling rate converter × 1 channel
Max. operating frequency: 1.0GHz Serial sound interface × 4 channels System CPU Interfaces
Arm® Cortex®-M33, single-core Storage interfaces Arm Debugger Cortex®-A55 1.0GHz DDR4/DDR3L (In line ECC)
(CoreSight™) NEON/VFP 16-bit × 1.6/1.3Gbps
Max. operating frequency: 200MHz USB 2.0 × 2 channels (Host only 1
Cache memory (Cortex®-A55) channel/Host-Function 1channel) Arm TrustZone I-L1$: 32KB w/Parity 1 × SPI Multi I/O
16ch DMAC D-L1$: 32KB w/ECC (4-bit DDR)
L1 instruction cache: 32KB SD host interface × 2 channels Cortex®-M33
Interrupt Controller L2$: 0KB SDHI (UHS-I)/MMC
L1 data cache: 32KB Multimedia card interface × 1 channel @200MHz
L3 cache: 256KB (Shared with SDHI) PLL/SSCG L3$: 256KB w/ECC
1 × USB2.0 Host
External memory Other peripheral functions Standby Memory 1 × USB2.0
Ability to connect DDR4-SDRAM / 16-bit timer × 8 channels (Sleep/Software/Module) Host / Function
RAM 128KB w/ECC
DDR3L-SDRAM via DDR dedicated bus I2C bus interface × 4 channels Timers 2 × 100/1000Mbps
Data bus width: 16 bits × 1 channel Serial communication interface with Video & Graphics Ether MAC*(#)
Video functions FIFO (SCIF) × 5 channels 8 × 16-bit MTU3*(#)
Image Scaling Unit
2 × I2C, 2 × I2C*
Video display interface: Serial communication interface (SCI) ×
Display Out (Parallel-IF*)(#) 2 × SCI 8/9-bit*
Digital parallel output × 1 channel 2 channels
2 × WDT* 5 × SCIF (UART)*(#)
Video input interface: SPI Multi I/O Bus Controller× 1 channel Camera In (MIPI CSI-2 4lane)
3 × RSPI*
MIPI CSI-2 × 1 channel (4bit Double data rate) Analog
2 × CAN-FD*
Video image processing functions Serial Peripheral Interface (RSPI) × 2 × 12-bit ADC(#) Security (option)
Secure Boot Device Unique ID GPIO*
(Resizer and Color Space / Color Format 3channels
Conversion) Gigabit Ethernet controller × 2 channels Crypto Engine JTAG Disable Audio
Controller area network (CAN) interface TRNG OTP 1Kbit 4 × SSI (I2S)*(#)
× 2 channels (support CAN FD) (#) There are 2 types in RZ/G2UL. [Type-2] RZ/G2LC pin compatible version 1 × SRC
12-bit A/D converter × 2 channels [Type-1] Full function version - No support: Display out, Parallel-IF
*Shared
Interrupt controller - This block diagram is Type-1. - 1×Ether MAC, 3×SCIF, 3×SSI
Clock generator (CPG): on-chip PLL
On-chip debug functionRZ/Five [RISC-V] (R9A07G043Fxx)
CPU core Other peripheral functions ¢ RZ/Five [RISC-V] (R9A07G043Fxx) block diagram
64bit RISC-V CPU Core AndesCore™ 16-bit timer × 8 channels
AX45MP Single core 1.0 GHz I2C bus interface × 4 channels System CPU Interfaces
Application Core Domain
Cache memory Serial communication interface with Debugger DDR4/DDR3L 16-bit × 1.6/1.3Gbps
AX45MP Single (1GHz)
L1 Instruction Cache: 32K Byte FIFO (SCIF) × 5 channels 16ch DMAC
With SIMD / FPU
1 × SPI Multi I/O (4-bit DDR)
L1 Data Cache: 32K Byte Serial communication interface (SCI) × Interrupt Controller I-L1$: 32KB, D-L1$: 32KB 2 × SDHI(UHS-I)/MMC
L2 Cache: 256K Byte 2 channels PLL/SSCG TCM (ILM/DLM): Total 128KB (1GHz) 1 × USB2.0 Host
External memory SPI Multi I/O Bus Controller × 1 channel L2$: 256KB 1 × USB2.0 Host / Function
Ability to connect DDR4-SDRAM / (4bit Double data rate) 2 × 100/1000
DDR3L-SDRAM via DDR dedicated bus Serial Peripheral Interface (RSPI) ×3 Timers Internal Memory Ether MAC*
Data bus width: 16 bits × 1 channel channels 1 × 32-bit MTU3 SRAM: 128KB 4 × I2C
Audio functions Gigabit Ethernet controller × 2 channels 8 × 16-bit MTU3 2 × SCI 8/9-bit (incl. IrDA)
Security (option)
Sampling rate converter × 1 channel Controller area network (CAN) interface 1 × WDT Secure Boot 5 × SCIF (UART)
Serial sound interface × 4 channels × 2 channels (support CAN FD) Crypto Engine 3 × RSPI
Storage interfaces 12-bit A/D converter × 2 channels Analog Secure JTAG 4 × SSIF2
Storage interfaces Interrupt controller 2 input 12-bit ADC (1 unit) TRNG 1 × SRC
USB 2.0 × 2 channels (Host only 1 Clock generator (CPG): on-chip PLL Thermal Sensor 2 × CAN-FD
OTP 1Kbit
channel/Host-Function 1channel) On-chip debug function GPIO
SD host interface × 2 channels
*: The 266-pin package has one channel of Package Information: 361-pin, 13 × 13mm PBGA (0.5mm pitch)
Multimedia card interface × 1 channel Gigabit Ethernet. 266-pin, 11 × 11mm PBGA (0.5mm pitch)
(Shared with SDHI)16-17
RZ/G Series Application
[HMI Application] The HMI can be made more expressive by making full use of the 3D graphics and video capabilities.
KIOSK/POS Terminal Measuring Equipment Inspection Device Medical Display Nurse Call System CNC Equipment Doorbell System Multifunction Printer
Building Automation Control Panel Digital Signage Industrial Display Surveillance Camera Handy Terminal Home Security Business Purpose Equipment
[IoT Application] Optimized for IoT devices by taking advantage of CPU performance, various interface functions, and security functions
Solar Inverter Secure Home Gateway EV Charger Industrial Gateway Infra Sensing Gateway Smart Agriculture Gateway
RZ Partner Ecosystem Solutions
Visit the webpage below for the latest information on RZ partner ecosystem.
https://www.renesas.com/products/microcontrollers-microprocessors/rz-mpus/rz-partner-solutionsRZ/A Series
RZ/A Series Roadmap
RZ/A1M
Cortex®-A9 (400MHz)
5MB, WXGA, 2D
RZ/A3UL RZ/A-next
RZ/A1H RZ/A1LU Cortex®-A55 (1GHz)
Cortex®-A9 (400MHz) Cortex®-A9 (400MHz) DDR3L/4, WXGA, MIPI-CSI
10MB, WXGA, 2D 3MB, XGA, JPEG RZ/A2M
Cortex®-A9 (528MHz)
RZ/A1L RZ/A1LC 4MB, XGA, 2D
Cortex®-A9 (400MHz) Cortex®-A9 (400MHz)
3MB XGA 2MB, XGA
2018 2019 2022 2023 CY
RZ/A Series Application
Intercoms White goods White goods Vending machines Digital signage Diagnostic panels Industrial panels
Barcode scanners Office equipment Image sensor Data communication modules Robot Biometrics Handwriting recognition input devices
(telematics, emergency communications)
Benefits of RZ/A Series — Develop like MCUs
RZ/A series MPUs retain the ease-of-use of Renesas MCUs due to rich integrated development environments, and deliver higher performance
than MCUs.18-19
Benefits of RZ/A3UL
64bit CPU@1GHz RTOS MPU
Choice of two memory I/Fs for different applications
– Octal-SPI Flash/Octal-SPI RAM: For simple and low cost PCB design
– DDR3L/DDR4: For high resolution HMI and camera use cases
Pin-compatible RZ/A3UL (RTOS) and RZ/G2UL (Linux) for easy migration
– The 361-pin package is pin-compatible between RZ/A3UL and RZ/G2UL
Benefits of RZ/A1 Group, and RZ/A2M MPUs
Eliminate the need to design a high-speed interface Include on-chip graphics display and camera input capabilities
Reduced mounting area
Reduced PCB cost
No DRAM procurement issues
Reduced EMI noise
DRP Library
RZ/A2M MPUs with DRP improve image processing performance by 10X over RZ/A1 MPUs
– Dynamically Reconfigurable Processor (DRP) technology accelerates image processing
– Enables hybrid e-AI solutions with DRP for image processing + CPU for inference
The RZ/A2M is designed around e-AI for smart appliances, network cameras, service robots, scanner products, and industrial equipment
requiring high-speed image processing. The RZ/A2M combines a general-purpose MPU with Renesas’ proprietary DRP technology for unique
hybrid processing for image recognition and machine vision (MV), and AI processing works in conjunction with the Cortex®-A9, which pre-
processes image data at high speed and extracts features for recognition target.¢ RZ/A3UL block diagram
RZ/A3UL Group
System CPU Interfaces
64-bit Arm® Cortex®-A55 (1 GHz, single core) Arm Debugger Cortex®-A55 1.0GHz DDR4/DDR3L (In line ECC)
16bit DDR3L/DDR4-1600 (in line ECC) (CoreSight™) NEON/VFP 16bit × 1.6/1.3Gbps
Octal-SPI Flash/RAM IF I - L1$: 32KB w/Parity SPI Multi I/O or Octa IF
16 ch DMAC D-L1$: 32KB w/ECC (4/8bit × 200Mbps)
Camera IF; MIPI-CSI2 (4 lanes) L2$: 0KB
Interrupt Controller (Cache: 64bit line x 32 entries)
Display IF; Parallel RGB888/RGB666 L3$ (Shared) : 256KB w/ECC
2x Gigabit Ethernet PLL/SSCG 1 × SDHI (UHS-I)/MMC
2x CAN (CAN-FD) Standby Memory 1 × SDHI (UHS-I)
2x USB2.0 (Host, Host/Peripheral) (Sleep/Module) RAM128KB w/ECC 1 × USB2.0 Host
2x SDHI (UHS-I, UHS-I/MMC)
1 × USB2.0
Timers LCD Controller + Resize Host / Function
1 × 32bit MTU3* Image Scaling Unit 2 × 100/1000Mbps
Ether MAC*
8 × 16bit MTU3* Display Out (Parallel-IF*)
3 × I2C*
2 × WDT* Camera In (MIPI-CSI2 4lane)
2 × SCI 8/9bit*
Analog Audio 5 × SCIF (UART)*
2 ×12bit ADC 4 × SSI (I2S)*
3 × RSPI*
2 × CAN-FD*
GPIO*
* Shared
¢ RZ/A2M block diagram
RZ/A2M Group
System CPU Interfaces
CPU (Arm® Cortex®-A9) DMAC 16ch Cortex®-A9 528 MHz I2C
Operating frequency: 528MHz 4ch
Interrupt Controller
Single-precision/double-precision FPU NEON FPU SCI
Arm® NEON™ PLL/SSCG 2ch
On-chip memory On-chip Debug Memory SCIF (UART)
4MB (JTAG/SWD) 5ch
SRAM: 4MB
Main graphics and camera input functions Standby RSPI
I CACHE: 32KB D Cache: 32KB 3ch
Video display controller (VDC6): 1 channel (Sleep/Software/Deep/Module)
L2 Cache: 128KB CAN-FD
LCD output: Max. WXGA 2ch
Screen superimposition: 3 layers Timers Ethernet MAC
Video input: Max. XGA Graphics
OSTM (100M: IEEE1588 v2)
CMOS camera input (CEU): 1 channel 32-bit × 3ch LVDS 2ch
VDC6 (LCDC)
MIPI-CSI2 interface: 1 channel MTU3 Timing Controller IMR-LS2 IrDA
Distortion compensation unit (IMR): 1 channel 32-bit × 1ch Digital Input Sprite Engine SSI (I2S)
2D graphics engine: 1 channel MTU3 4ch
Sprite engine: 1 channel 16-bit × 8ch CMOS Camera I/F 2D Graphics Engine
MIPI Camera I/F JPEG Codec Engine SPDIF
JPEG coding engine: 1 channel PWM 1ch
32-bit × 8ch
Main memory interface functions
WDT BSC (E×t. Bus I/F)
NOR flash, SDRAM, NAND flash Security (option)
Serial flash: 1-bit/4-bit/8-bit: 1 channel, 8-bit: 1 channel RTC Secure Boot HyperFlash™ / HyperRAM™
(ability to run stored programs directly)
Crypto Engine OctaFlash™ / OctaRAM™
SD/MMC host interface: 2 channels DRP (option)
Main communication functions (Dynamically Reconfigurable Processor) SPI Multi I/O (DDR)
TRNG (1,4 or 8bit width)
USB 2.0 High Speed: 2 channels (Host/Function switchable)
10M/100M EtherMAC: 2 channels Device Unique ID NAND Flash I/F
(ONFI1.0, ECC)
SCIF: 5 channels JTAG Disable USB2.0
I2C: 4 channels HS 2ch Host/Peripheral/OTG
SSI: 4 channels SDHI (UHS-I)/MMC
RSPI: 3 channels 2ch
CAN-FD: 2 channels GPIO
Optional functions
DRP (Dynamically Reconfigurable Processor) Analog
Package
ADC
176-LFBGA (13mm×13mm, 0.8mm pitch) 12-bit × 8ch
256-LFBGA (11mm×11mm, 0.5mm pitch)
272-FBGA (17mm×17mm, 0.8mm pitch)
324-FBGA (19mm×19mm, 0.8mm pitch)20-21
¢ RZ/A1H,and RZ/A1M block diagram
RZ/A1H Group and RZ/A1M Group (Pin Compatible)
Memory CPU Interfaces
CPU (Arm® Cortex®-A9) SRAM Cortex®-A9 400MHz 10/100 Ether MAC
Operating frequency: 400MHz A1H: 10MB/A1M: 5MB
Single-precision/double-precision FPU SRAM L2 Cache NEON FPU USB2.0
Arm® NEON™ 128 KB HS 2ch Host/Func
On-chip memory Cache NAND Flash
32 KB + 32 KB Timers I/F
RZ/A1H: 10MB
MTU2 External Bus 32-bit ROM,
RZ/A1M: 5MB SRAM,
Main graphics and camera input functions System 16-bit × 5ch
WDT SDRAM, PCMCIA
Video display controller (VDC5): 2 channels DMAC 16ch 8-bit × 1ch SPI Multi
LCD output: Max. WXGA OS Timer 2ch
Screen superimposition: 4 layers Interrupt Controller SCIF RSPI
32-bit × 2ch
Video input: Max. XGA (CVBS analog input supported) Clock Generation PWM Timer 8ch 5ch
CMOS camera input (CEU): 1 channel with SSCG 16ch IC
2
IEBus
PAL/NTSC decoder (DVDEC): 2 channels 4ch 1ch
JTAG Debug Real-Time CLK
Distortion compensation unit (IMR): 1 channel SSI (I2S) SPDIF
Open VG accelerator: 1 channel Customer Unique ID* 6ch 1ch
Graphics SDHI MMC
JPEG coding engine: 1 channel 2ch 1ch
Audio Video Display Controller
Main memory interface functions 2ch CAN MOST50
NOR flash, SDRAM, NAND flash SCUX 4ch ASRC OpenVG 1.1 5ch 1ch
QSPI serial flash: 2 channels (ability to run stored programs directly) Enhanced eng. Smart Card I/F
SD host interface: 2 channels CDROM DEC PAL/NTSC 2ch
MMC host interface: 1 channel dec. 2ch IrDA LIN Master
Sound Generator
Main communication functions CMOS Camera I/F 1ch 2ch
USB 2.0 High Speed: 2 channels (Host/Function switchable) 1ch Ethernet AVB
10M/100M EtherMAC: 1channel Analog Fish Eye Correction
SCIF: 8 channels ADC 2ch
12-bit × 8ch JPEG Engine
I2C: 4 channels
1ch
SSI: 6 channels * =Option
RSPI: 5 channels
Ethernet AVB: 1 channel
CAN: 5 channels
Package
256-LFBGA (11mm × 11mm,0.5mm pitch)
256-LFQFP (28mm × 28mm,0.4mm pitch)
324-FBGA (19mm × 19mm,0.8mm pitch)
¢ RZ/A1LU block diagram
RZ/A1LU Group
Memory CPU Interfaces
CPU (Arm® Cortex®-A9) SRAM Cortex®-A9 400MHz 10/100 Ether MAC
Operating frequency: 400MHz 3MB
Single-precision/double-precision FPU SRAML2 Cache NEON FPU CAN
128 KB 2ch
Arm® NEON™ USB2.0
Cache
On-chip memory 32 KB + 32 KB Timers HS 2ch Host/Func
3MB MTU2 External Bus 32-bit
Main graphics and camera input functions System 16-bit × 5ch ROM, SRAM,
WDT SDRAM, PCMCIA
LCD controller (VDC5): 1 channel
DMAC 16ch 8-bit × 1ch SPI Multi
LCD output: Max. WXGA 1ch
Interrupt Controller OS Timer
Screen superimposition: 3 layers 32-bit × 2ch SCIF RSPI
Video input: Max. XGA Clock Generation 5ch 3ch
Real-Time CLK
CMOS camera input (CEU): 1 channel with SSCG I2C
4ch
JPEG coding engine: 1 channel JTAG Debug Graphics SSI (I2S) SPDIF
Main memory interface functions
Customer Unique ID* Video Display Controller 4ch 1ch
NOR flash, SDRAM 1ch SDHI MMC
QSPI serial flash: 1 channel (ability to run stored programs directly) CMOS Camera I/F 2ch 1ch
Audio
SD host interface: 2 channels 1ch Smart Card I/F
MMC host interface: 1 channel SCUX 4ch ASRC JPEG Engine 2ch
1ch IrDA
Main communication functions 1ch
USB 2.0 High Speed: 2 channels (Host/Function switchable) Analog
ADC Ethernet AVB
10M/100M EtherMAC: 1channel
12-bit × 8ch
SCIF: 5 channels
I2C: 4 channels * =Option
SSI: 4 channels
RSPI: 3 channels
Ethernet AVB: 1 channel
CAN: 2 channels
Package
176-LFBGA (8mm × 8mm,0.5mm pitch)
176-LFQFP (24mm × 24mm,0.5mm pitch)
208-LFQFP (28mm × 28mm,0.5mm pitch)¢ RZ/A1L, RZ/A1LC block diagram
RZ/A1L, RZ/A1LC Group
Memory CPU Interfaces
CPU (Arm® Cortex®-A9) SRAM Cortex®-A9 400MHz 10/100 Ether MAC
Operating frequency: 400MHz A1L: 3 MB/A1LC: 2 MB
Single-precision/double-precision FPU SRAM L2 Cache NEON FPU USB2.0
128 KB HS 2ch Host/Func
Arm® NEON™ External Bus 32-bit
Cache
On-chip memory 32 KB + 32 KB Timers ROM, SRAM,
RZ/A1L: 3MB MTU2 SDRAM, PCMCIA
RZ/A1LC: 2MB System 16-bit × 5ch SPI Multi
1ch
Main graphics and camera input functions WDT
DMAC 16ch 8-bit × 1ch SCIF RSPI
LCD controller (VDC5): 1 channel 5ch 3ch
Interrupt Controller OS Timer
LCD output: Max. WXGA 32-bit × 2ch I2C IEBus*
Screen superimposition: 3 layers Clock Generation 4ch 1ch
with SSCG Real-Time CLK
Video input: Max. XGA SSI (I2S) SPDIF
CMOS camera input (CEU): 1 channel JTAG Debug 4ch 1ch
Graphics
Main memory interface functions SDHI MMC
Audio Video Display Controller 2ch 1ch
NOR flash, SDRAM, NAND flash 1ch
QSPI serial flash: 1 channel (ability to run stored programs directly) CAN MOST50*
SCUX 4ch ASRC CMOS Camera I/F 2ch 1ch
SD host interface: 2 channels 1ch
CDROM DEC* Smart Card I/F
MMC host interface: 1 channel 2ch
Main communication functions IrDA LIN Master*
Analog
USB 2.0 High Speed: 2 channels (Host/Function switchable) 1ch 1ch
10M/100M EtherMAC: 1 channel ADC
12-bit × 8ch
SCIF: 5 channels
I2C: 4 channels * RZ/A1L Group specification only.
SSI: 4 channels
RSPI: 3 channels
CAN: 2 channels
Package
176-LFBGA (8mm × 8mm,0.5mm pitch)
176-LFQFP (24mm × 24mm,0.5mm pitch)
208-LFQFP (28mm × 28mm,0.5mm pitch)
233-FBGA (15mm × 15mm, 0.8mm pitch)You can also read
