All Programmable Technologies in Academia - Patrick Lysaght Senior Director
←
→
Page content transcription
If your browser does not render page correctly, please read the page content below
All Programmable Technologies
in Academia
Patrick Lysaght
Senior Director
© Copyright 2013 Xilinx
.
Agenda
Xilinx: a Generation Ahead at 28nm
The “Industrial Internet”
~ aka The Internet of Things
Academia in Transition
The “Post-PC” Era
~ The rising importance of embedded SOCs
ZED: Zynq®-7000 All programmable SoCs in Education
Vivado® Design Suite: a CAD suite for All Programmable
Systems
Page 2 © Copyright 2013 Xilinx
.
A Generation Ahead at 28nm
28nm Xilinx at 28nm
Portfolio: All Programmable FPGAs, SoCs and 3D ICs today
Product: Extra node of performance, power and integration
Productivity: Unmatched time to integration and implementation
Page 3 © Copyright 2013 Xilinx
.
The First System Optimized FPGAs
FPGAs
Scalable and System Optimized Architecture
In production now
Virtex-7 2x bandwidth & capacity, 35% power, SerDes
Kintex-7 35% power, 45% faster logic, 2x DSP
Artix-7 15% faster and $5-$10 lower system BOM
Page 4 © Copyright 2013 Xilinx
.
The First All Programmable 3D IC
7V2000T in production now
2x capacity, 2x bandwidth
4x more 28Gbps SerDes channels
Only programmable homogeneous and heterogeneous 3D IC
Volume ramped significantly in Q2, 2012
Page 5 © Copyright 2013 Xilinx
.
Heterogeneous Integration
Highest bandwidth FPGA with 2.78 Tb/s serial
connectivity
Electrically-isolated 28G transceivers for optimal
signal integrity
Homogeneous
digital logic Different silicon
processes
28G
Transceivers
28G
Transceivers
Passive interposer Noise isolation
13G
Transceivers
Page 6 © Copyright 2013 Xilinx
.
The First All Programmable SoC
All devices in production now
>25% ARM performance, 45% logic performance
Highest productivity with Vivado HLS, ARM ecosystem
All Major OS’s supported and in use, 20 unique dev boards
350+ Customers actively designing,100+ partners
Shipped 20,000 devices, 4000 development boards
Page 7 © Copyright 2013 Xilinx
.
The First SoC Strength Design Suite
In production now
Built from the ground up for the next decade of devices
Now used for ~50% of 28nm designs, 100% of 3D ICs
Delivering 4x productivity, turning months to weeks
Page 8 © Copyright 2013 Xilinx
.
Industry Mandates
Programmable
Imperative
Programmable
Systems
Integration
Insatiable
Intelligent
Bandwidth
Page 9 © Copyright 2013 Xilinx
.
Insatiable Intelligent Bandwidth
Overall IP Traffic
in exabytes per month:
CAGR 29%
We Will Soon Live in a 100 Gb World
Page 10 © Copyright 2013 Xilinx
.IPV6 enables Dramatic M2M Growth
IPv6-Capable Fixed Devices by Device type, in Millions, 2011-2016
120.5% CAGR in Machine-to-Machine traffic starting from 2012
Source: The Zettabyte Era,
Cisco VNI: Forecast and Methodology, 2011-2016
© Copyright 2013 Xilinx
.The Internet of Things
The internet of
things was born
between 2008
and 2009
when for the first time
more “things or objects”
were connected to the
Internet than people
http://www.cisco.com/web/about/ac79/docs/innov/IoT_IBSG_0411FINAL.pdf
Page 12 © Copyright 2013 Xilinx
.IOT ... an Internet dominated by networked
“things” (not PCs, cell phones and tablets)
The “Internet of Things”, is “the general idea of things, especially
everyday objects, that are readable, recognizable, locatable,
addressable, and controllable via the Internet …”
US National Intelligence Council
Today, more than 20 percent of Internet traffic originates from non-
computing devices
Predictions are that by 2020, as many as 50 billion machines will be
plugged into the Internet
Tremendous opportunities for multi-disciplinary teaching research in
networked, embedded systems
Page 13 © Copyright 2013 Xilinx
.Re-target Internet technologies for the benefit
of big industry
Source: Industrial Internet: Pushing the Boundaries of Minds and Machines
Peter C. Evans and Marco Annunziata, GE, November 26, 2012
Page 14 © Copyright 2013 Xilinx
.Scale up the vision on a grand scale …
and we get the “Industrial Internet”
Source: Industrial Internet: Pushing the Boundaries of Minds and Machines
Peter C. Evans and Marco Annunziata, GE, November 26, 2012
Page 15 © Copyright 2013 Xilinx
.Illustrative Classes of Large Rotating Machines
aka “Big Things that Spin”
Source: Industrial Internet: Pushing the Boundaries of Minds and Machines
Peter C. Evans and Marco Annunziata, GE, November 26, 2012
Page 16 © Copyright 2013 Xilinx
.Motivation: “The power of 1%”
Source: Industrial Internet: Pushing the Boundaries of Minds and Machines
Peter C. Evans and Marco Annunziata, GE, November 26, 2012
Page 17 © Copyright 2013 Xilinx
.The Merger of Industrial Revolution and Internet
Revolution is a Complex Vision
These opportunities have their doppelgängers …
Cyber security challenge to critical infrastructure
Shortage of high-quality electricity for exploding data center
demand
Challenge of energy-efficient, high performance computing
– Especially high performance, embedded computing
Immediate skills shortage
– From “digital mechanical engineers” to the data analytics scientists
© Copyright 2013 Xilinx
.Meanwhile, Academia is in Transition …
Prof John Hennessy, President of Stanford University,
says that this change is due to the “coming tsunami in
educational technology”.
Page 19 © Copyright 2013 Xilinx
.Agents of Change in Educational Technology
New delivery formats Search engines, etc
– edX, Coursera, Udacity – Google, Wikipedia
– Khan Academy,
Codeacademy Social media
– Peer interaction &
Broadband Internet learning
Video everywhere Open Source
– YouTube – Software & textbooks
E-Books Rapid curriculum expansion
– Especially in electronics
Printing-on-Demand & computing
Page 20 © Copyright 2013 Xilinx
.Characteristics of The Post-PC ERA
Universal mobility & connectivity
The Internet of people is expanding to the “Internet of things”
Computing has become an immersive, connected experience
The “Cloud” underpins the mobile experience
Embedded systems using systems-on-chip (SOC) are the key
technology enabler of the Post-PC era
– They are drivers for major changes in engineering education
Page 21 © Copyright 2013 Xilinx
.Enabling Post-PC ERA Engineering Education
The PC is not dead – it remains a powerful tool for more
competent users
But non-PC, consumer, electronic devices proliferate
– These devices have more specialized functionalities and more intuitive
interfaces, for example smart phones, tablets, E-readers, HDTVs
– Embedded heterogeneous SOCs will drive of the Industrial Internet
The curriculum in Electronics and Computer Engineering must
change to meets the need to teach and research the challenges
of engineering of SOCs in embedded systems
Education for SOC Engineering is Vital
Page 22 © Copyright 2013 Xilinx
.The Emerging Educational Challenges
Coping with curriculum expansion driven by the rise of SOC
technology in embedded systems in the post PC era
Educating a generation of engineers in systems design and
integration
Educating students to understand and practice design re-use by
using third-party IP and designing for re-use by creating their
own re-usable IP
Introducing High-level Synthesis from traditional software
programming languages such as C, C++, SystemC
Page 23 © Copyright 2013 Xilinx
.An Image Processing Example
The Back Projection algorithm is
used in variety of tomography
applications, including CAT
scanners
Takes raw data from a scan at
different angles and reconstructs
an image based on that data
From Datasets re-construct the
256
image
Page 24 © Copyright 2013 Xilinx
.Complete Design Consumes 2 Watts !!!
ARM® CoreSight™ Multi-core & Trace Debug
NEON™/FPU Engine NEON™/FPU Engine
ACP
ACP AXI4 interconnect
Cortex™-A9 MP Core™ Cortex™-A9 MP Core™ m
32/32 KB I/D Caches 32/32 KB I/D Caches s s s s
512 KB L2 Cache Snoop Control Unit (SCU)
Timers / Counters 256 KB On-Chip Memory
m m m m
General Interrupt Controller DMA Configuration
AXI_DMA AXI_DMA
s s
Memory AMBA® Switches
Accelerator Accelerator
s s
m
m m m m
HDMI AXI4 Lite interconnect
Output
Page 25 © Copyright 2013 Xilinx
.The Next Step: “Design for Re-use”
ARM® CoreSight™ Multi-core & Trace Debug
NEON™/FPU Engine NEON™/FPU Engine
ACP
ACP AXI4 interconnect
Cortex™-A9 MP Core™ Cortex™-A9 MP Core™ m
32/32 KB I/D Caches 32/32 KB I/D Caches s s s s
512 KB L2 Cache Snoop Control Unit (SCU)
Timers / Counters 256 KB On-Chip Memory
m m m m
General Interrupt Controller DMA Configuration
AXI_DMA AXI_DMA
s s
Memory AMBA® Switches
Accelerator Accelerator
s s
m
m m m m
HDMI AXI4 Lite interconnect
Output
These are the only new IP blocks
in the design
Page 26 © Copyright 2013 Xilinx
.Zynq-7000: ALL PROGRAMMABLE Platform for
Post-PC Era Engineering Education
Complete ARM®-based Processing System
– Dual ARM Cortex™-A9 MPCore™, processor centric
– Integrated memory controllers & peripherals
– Fully autonomous to the Programmable Logic Processing Memory 7 Series
Interfaces Programmable
System
Logic
Tightly Integrated Programmable Logic
– Used to extend Processing System Common
Peripherals
ARM® Common
Peripherals
Dual Cortex-A9
– High performance ARM AXI interfaces MPCore™ System Custom
Peripherals
– Scalable density and performance
Common Accelerators
Custom Accelerators
Flexible Array of I/O
– Wide range of external multi-standard I/O
– High performance integrated serial transceivers
– Analog-to-Digital Converter inputs
Best-in-class Embedded Processing and FPGA Technologies
Page 27 © Copyright 2013 Xilinx
.Embedded Processing Leader for Post-PC Era
SOC Designs
ARM is the world’s leading semiconductor IP company
800 processor licenses sold to more than 250 companies
Over 20 billion ARM based chips shipped to date
Two billion chips based on ARM RISC processor technology
shipped during the second quarter of 2012*
In contrast:
– Fewer than 100 million worldwide PC shipments in Q2 2012**
* Source www.arm.com ; ** Source Gartner
Page 28 © Copyright 2013 Xilinx
.Zed Board: Zynq in Education and Development
Low cost Zynq Evaluation and Development Kit (XC7Z020)
Open source SW and IP
– Linux
– Eclipse based IDE
– Vivado HLS: C to FPGA
– Reference designs
See zedboard.org
Configurable levels of abstraction for the first-time, novice user,
or the most advanced researcher
Page 29 © Copyright 2013 Xilinx
.ZRobot Robot Example
ZED board enabled Robot
… wirelessly controlled
by an Android tablet
… with full video relay
from ZRobot cameras
to tablet display
See the demo at the
Xilinx Booth
Page 30 © Copyright 2013 Xilinx
.Next Steps: ZRobot- Mark 2
Android App IE Webpage
Remote Video
Remote Control Advanced Motor
Robotics/Industrial Control
RTOS
Linux
Boa Webserver OpenCV
MJPEG Encoding Computer Vision
WIFI DDR 3
Access Point Car Wheels
DDR Memory Controller Programmable Logic
Processing
System Robotic ARMs
Motor Control
AMBA® Switches PWM
GE
APU
Dual ARM Surround
Status LEDs GPIO Video
Cortex-A9 CCD Cameras
Pre-processing
SD Card SDIO
AMBA® Switches
Sensor Sensor Farm
Interfaces
AXI4 Interconnect (Lite)
S_AXI_HP 64 bit Voice
Processing
S_AXI_GP 32b bit
ZED Board
Face Detection Sensor & Peripheral
Lane Detection Reference Designs
Computer Vision
Page 31 © Copyright 2012
2013 Xilinx
.Xilinx Tools: From Vision to Deployment
More Than Just Silicon – A Comprehensive Platform Offering
Page 32 © Copyright 2013 Xilinx
.Vivado Design Reuse:
Hierarchical Design Flows
Design Reuse Flow enables
parallel implementation
for Team Design
– Place & Route modules out
of context from top level design
– Iterate on these modules without
overhead of the full design
– Assemble results in context of
top for exact preservation
Package IP and reuse in new designs
– Reuse module as a pre-verified
placed & routed result
Page 33 © Copyright 2013 Xilinx
.Package Designs into System-Level IP for Reuse
Standardized IP-XACT
representation
Vivado IP Integrator
Memory
Interface
Memory Interfaces
Source (C, RTL, IP, etc)
Processor
PCIe Display
Simulation Models System
Xilinx IP
Documentation IP Packager
Embedded Interconnect
Example Designs 3rd Party IP User IP Xilinx IP 3rd Party IP
Test Bench Processing Datapath
User IP
Share IP within your team, project or company
3rd party IP delivered with a common look and feel
Reuse in different designs
Reuse IP at any point in the implementation process
– Source, placed, or placed and routed
Reuse multiple times
Page 34 © Copyright 2013 Xilinx
.Seamless IP Access and Customization
Integrated IP catalog
– Powerful search capabilities
– Single-click access to IP functionality
and collateral
IP customization and generation
– Instant access to customization GUI
– Generate output products in
project or remote directory
– Customize graphically or via Tcl
Page 35 © Copyright 2013 Xilinx
.IP Packager: IP-XACT
IEEE 1685
IP-XACT is an industry standard way to represent
data about IP (meta-data)
– Port information
– Latency
– Configurable parameters
– Etc.
ASCII XML based
Enables IP to be used in multiple vendor tools flows
Page 36 © Copyright 2013 Xilinx
.Extensible IP Catalog: Add Packaged IP
1. Unzip IP to a local directory
2. Right-click on IP Catalog
3. Add directory to IP Catalog
Page 37 © Copyright 2013 Xilinx
.Vivado IP Integrator
A graphical design environment to enable rapid and accurate
connection of complex IP
– Connections made at the interface level, not the individual signal level
– Automatic setting and propagation of IP parameters
– Automated generated of RTL
– Full support for arbitrary levels of design hierarchy
– Capable of processor-based or non-processor based design creation
Tight integration with Vivado IP Packager flow for rapid IP and
subsystem reuse
Page 38 © Copyright 2013 Xilinx
.IP Integrator User Interface
Hierarchy Support
System Hierarchy Interface Connections
View with Real-time DRCs
TCL Console
Page 39 © Copyright 2013 Xilinx
.Vivado High-Level Synthesis Design Flow
Vivado HLS
Function
C Specification
C Verification
Starts at C C C
Design Test Bench
– C
– C++ C Synthesis
– SystemC
Architecture RTL
Produces RTL Design
– Verilog
RTL Verification
– VHDL
C Behavioral
– SystemC Wrapper Verification
Automates Flow IP Block
– RTL Verification Packaging Vivado IP Packager
– IP Packaging Vivado IP Integrator
IP Package
System Generator
Page 40 © Copyright 2013 Xilinx
.Function versus Architecture
Function
Sequential
void top (
int& dout1,
int& dout2,
int din1,
int din2
) {
dout1 = din1+din2;
dout2 = din1*din2;
}
Architecture Datapath
State machine
Interface always @(posedge clk)
always @(posedge clk) case (state)
module top (dout1,dout2, begin RST:
din1,din2, if (rst == 1’b1) begin
ovld,ivld, stateZynq and Vivado in Education
Zynq®-7000 All Programmable SoCs integrate state-of-the-art
FPGA technology with best-in-class embedded CPUs to define a
new class of ALL PROGRAMMABLE SOC devices which are ideal
for teaching and research
Vivado® Design Suite is a new tool suite based on hierarchical,
design re-use and high-level synthesis which has been designed
for the next decade of programmable systems integration
Teaching and researching the principles and practice of SOC
engineering is now possible at the undergraduate and graduate
levels
Page 42 © Copyright 2013 Xilinx
.Promoting & Disseminating Best Practice
The collective opportunity is huge but the complexity is non-
trivial
– Especially for integrated multi-disciplinary teaching and research
The individual contribution is crucial
– But the challenge can be overwhelming in isolation
Effective collaboration and re-use are essential
– Not only to promote rapid dissemination
– But also rapid, widespread reuse of best practice
The Internet is both the challenge and the opportunity
Page 43 © Copyright 2013 Xilinx
.XUP’s Charter
Xilinx is a learning company
– We provide enabling technologies not vertical products so we are
constantly learning from our customers and partners
XUP adopts the same approach with our academic partners
We strive to …
– Provide the best possible enabling technology
– Identify and support best teaching and research practices
– Partner to disseminate best practice as widely as possible
So please, give us your feedback
– We need your good ideas!
Page 44 © Copyright 2013 Xilinx
.Closing Thoughts …
“Don’t believe everything you read on the Internet.”
Abraham Lincoln,
U.S. President
Page 45 © Copyright 2013 Xilinx
.Enabling Technologies for Academia
Xilinx: All Programmable leadership at 28nm
The Internet is both the opportunity and the challenge
Zynq and Vivado will enable Professors and students to
28nm
reach new levels of creativity and collaboration in their
teaching and research
Page 46 © Copyright 2013 Xilinx
.Thank You
Page 47 © Copyright 2013 Xilinx
.You can also read
