Lecture Notes in Electrical Engineering Volume 73
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Lecture Notes in Electrical Engineering Volume 73 For other titles published in this series, go to www.springer.com/series/7818
Guy Gogniat Dragomir Milojevic Adam Morawiec Ahmet Erdogan Editors Algorithm- Architecture Matching for Signal and Image Processing Best papers from Design and Architectures for Signal and Image Processing 2007 & 2008 & 2009
Editors
Guy Gogniat Adam Morawiec
Lab-STICC-CNRS, UMR 3192, Centre de ECSI
Recherche Av. de Vignate 2
Université de Bretagne Sud – UEB 38610 Gières
BP 92116 France
56321 Lorient Cedex adam.morawiec@ecsi.org
France
guy.gogniat@univ-ubs.fr
Ahmet Erdogan
Dragomir Milojevic School of Engineering
Université libre de Bruxelles The University of Edinburgh
CP 165-56, Av. FD Roosevelt 50 Mayfield Road
1050 Bruxelles EH9 3JL Edinburgh
Belgium United Kingdom
dmilojev@ulb.ac.be ahmet.erdogan@ee.ed.ac.uk
ISSN 1876-1100 e-ISSN 1876-1119
ISBN 978-90-481-9964-8 e-ISBN 978-90-481-9965-5
DOI 10.1007/978-90-481-9965-5
Springer Dordrecht Heidelberg London New York
Library of Congress Control Number: 2010938790
© Springer Science+Business Media B.V. 2011
No part of this work may be reproduced, stored in a retrieval system, or transmitted in any form or by
any means, electronic, mechanical, photocopying, microfilming, recording or otherwise, without written
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Cover design: VTEX, Vilnius
Printed on acid-free paper
Springer is part of Springer Science+Business Media (www.springer.com)Preface
Advances in signal and image processing together with increasing computing power
are bringing mobile technology closer to applications in a variety of domains like
automotive, health, telecommunication, multimedia, entertainment and many oth-
ers. The development of these leading applications, involving a large diversity of
algorithms (e.g. signal, image, video, 3D, communication, cryptography) is classi-
cally divided into three consecutive steps: a theoretical study of the algorithms, a
study of the target architecture, and finally the implementation. Such a linear design
flow is reaching its limits due to intense pressure on design cycle and strict perfor-
mance constraints. The approach, called Algorithm-Architecture Matching, aims to
leverage design flows with a simultaneous study of both algorithmic and architec-
tural issues, taking into account multiple design constraints, as well as algorithm and
architecture optimizations, that couldn’t be achieved otherwise if considered sepa-
rately. Introducing new design methodologies is mandatory when facing the new
emerging applications as for example advanced mobile communication or graphics
using sub-micron manufacturing technologies or 3D-Integrated Circuits. This di-
versity forms a driving force for the future evolutions of embedded system designs
methodologies.
The main expectations from system designers’ point of view are related to meth-
ods, tools and architectures supporting application complexity and design cycle re-
duction. Advanced optimizations are essential to meet design constraints and to en-
able a wide acceptance of these new technologies.
This book presents a collection of selected contributions addressing different as-
pects of Algorithm-Architecture Matching approach ranging from sensors to ar-
chitectures design. The scope of this book reflects the diversity of potential algo-
rithms, including signal, communication, image, video, 3D-Graphics implemented
onto various architectures from FPGA to multiprocessor systems. Several synthe-
sis and resource management techniques leveraging design optimizations are also
described and applied to numerous algorithms.
The contributions of this book are split into three parts addressing major issues
when designing embedded systems. The first part proposes key contributions in the
domain of architectures for embedded applications and especially for image and
vvi Preface
telecommunication processing. The second part focuses on data acquisition and de-
sign techniques for embedded systems. First, an optimized sensor for image acqui-
sition is detailed. Then several multiplication and division operators are described.
The end of this part proposes several contributions in the domain of partial and dy-
namic reconfiguration for signal and image processing. This technology leads to
complex design issues which are addressed in this chapter. The third part targets
embedded systems design. RTOS for embedded systems and scheduling techniques
are first addressed. Finally CAD tools for signal and image processing are detailed.
The coverage of this book is large and provides an in-depth analysis of existing tech-
niques and methodologies to design embedded systems targeting image and signal
processing.
Guy Gogniat
Dragomir Milojevic
Adam Morawiec
Ahmet ErdoganContents
Part 1 Architectures for Embedded Applications
Lossless Multi-Mode Interband Image Compression and Its Hardware
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Xiaolin Chen, Nishan Canagarajah, and Jose L. Nunez-Yanez
Efficient Memory Management for Uniform and Recursive Grid Traversal 27
Tomasz Toczek and Stéphane Mancini
Mapping a Telecommunication Application on a Multiprocessor
System-on-Chip . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Daniela Genius, Etienne Faure, and Nicolas Pouillon
Part 2 Data Acquisition and Embedded Systems
A Standard 3.5T CMOS Imager Including a Light Adaptive System for
Integration Time Optimization . . . . . . . . . . . . . . . . . . . . . 81
Gilles Sicard, Estelle Labonne, and Robin Rolland
Approximate Multiplication and Division for Arithmetic Data Value
Speculation in a RISC Processor . . . . . . . . . . . . . . . . . . . . 95
Daniel R. Kelly, Braden J. Phillips, and Said Al-Sarawi
RANN: A Reconfigurable Artificial Neural Network Model for Task
Scheduling on Reconfigurable System-on-Chip . . . . . . . . . . . . 117
Daniel Chillet, Sébastien Pillement, and Olivier Sentieys
A New Three-Level Strategy for Off-Line Placement of Hardware Tasks
on Partially and Dynamically Reconfigurable Hardware . . . . . . . 145
Ikbel Belaid, Fabrice Muller, and Maher Benjemaa
End-to-End Bitstreams Repository Hierarchy for FPGA Partially
Reconfigurable Systems . . . . . . . . . . . . . . . . . . . . . . . . . 171
Jérémie Crenne, Pierre Bomel, Guy Gogniat, and Jean-Philippe Diguet
viiviii Contents
Part 3 Embedded Systems Design
SystemC Multiprocessor RTOS Model for Services Distribution on
MPSoC Platforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Benoît Miramond, Emmanuel Huck, Thomas Lefebvre, and François
Verdier
A List Scheduling Heuristic with New Node Priorities and Critical Child
Technique for Task Scheduling with Communication Contention . . 217
Pengcheng Mu, Jean-François Nezan, and Mickaël Raulet
Multiprocessor Scheduling of Dataflow Programs within the
Reconfigurable Video Coding Framework . . . . . . . . . . . . . . . 237
Jani Boutellier, Christophe Lucarz, Victor Martin Gomez, Marco
Mattavelli, and Olli Silvén
A High Level Synthesis Flow Using Model Driven Engineering . . . . . . 253
Sébastien Le Beux, Laurent Moss, Philippe Marquet, and Jean-Luc
Dekeyser
Generation of Hardware/Software Systems Based on CAL Dataflow
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275
Richard Thavot, Romuald Mosqueron, Julien Dubois, and Marco
Mattavelli
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293Contributors
Said Al-Sarawi CHiPTec, Centre for High Performance Integrated Technologies
and Systems, The University of Adelaide, Adelaide, Australia,
alsarawi@eleceng.adelaide.edu.au
Ikbel Belaid University of Nice-Sophia Antipolis/LEAT-CNRS, 250 rue Albert
Einstein, 06560 Valbonne, France, Ikbel.Belaid@unice.fr
Maher Benjemaa National Engineering School of Sfax/Research Unit ReDCAD,
Sfax, Tunisia, Maher.Benjemaa@enis.rnu.tn
Sebastien Le Beux Institut des Nanotechnologies de Lyon, Ecole Centrale de
Lyon, 36, Avenue Guy de Collongue, 69134 Ecully Cedex, France,
Sebastien.Le-Beux@ec-lyon.fr
Pierre Bomel LAB-STICC, Université Européenne de Bretagne, Lorient, France,
pierre.bomel@univ-ubs.fr
Jani Boutellier Computer Science and Engineering Laboratory, University of
Oulu, Oulu, Finland, jani.boutellier@ee.oulu.fi
Nishan Canagarajah University of Bristol, Bristol, UK,
Nishan.Canagarajah@bristol.ac.uk
Xiaolin Chen University of Bristol, Bristol, UK, Xiaolin.Chen@bristol.ac.uk
Daniel Chillet University of Rennes 1, IRISA/INRIA, BP 80518, 6 rue de Keram-
pont, F22305 Lannion, France, Daniel.Chillet@irisa.fr
Jérémie Crenne LAB-STICC, Université Européenne de Bretagne, Lorient, France,
jeremie.crenne@univ-ubs.fr
Jean-Luc Dekeyser LIFL and INRIA Lille Nord-Europe, Parc Scientifique de
la Haute Borne, Park Plaza, Bât A, 40 avenue Halley, Villeneuve d’Ascq 59650,
France, Jean-Luc.Dekeyser@lifl.fr
Jean-Philippe Diguet LAB-STICC, Université Européenne de Bretagne, Lorient,
France, jean-philippe.diguet@univ-ubs.fr
ixx Contributors Julien Dubois Laboratoire LE2I, Université de Bourgogne, 21000 Dijon, France, julien.dubois@u-bourgogne.fr Etienne Faure SoC Department, LIP6, 4 place Jussieu, 75252 Paris Cedex, France, etienne.faure@lip6.fr Daniela Genius SoC Department, LIP6, 4 place Jussieu, 75252 Paris Cedex, France, daniela.genius@lip6.fr Guy Gogniat LAB-STICC, Université Européenne de Bretagne, Lorient, France, guy.gogniat@univ-ubs.fr Victor Martin Gomez Computer Science and Engineering Laboratory, University of Oulu, Oulu, Finland, victor.martin@ee.oulu.fi Emmanuel Huck ETIS Laboratory, UMR CNRS 8051, Université de Cergy- Pontoise/ENSEA, 6, avenue du Ponceau, 95014 Cergy-Pontoise, France, huck@ensea.fr Daniel R. Kelly CHiPTec, Centre for High Performance Integrated Technologies and Systems, The University of Adelaide, Adelaide, Australia, dankelly@eleceng.adelaide.edu.au Estelle Labonne TIMA Laboratory (CNRS, Grenoble INP, UJF), Grenoble, France Thomas Lefebvre ETIS Laboratory, UMR CNRS 8051, Université de Cergy- Pontoise/ENSEA, 6, avenue du Ponceau, 95014 Cergy-Pontoise, France, lefebvre@ensea.fr Christophe Lucarz Microelectronic Systems Laboratory, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland, christophe.lucarz@epfl.ch Stéphane Mancini GIPSA-lab, INPG-CNRS, 961 rue de la Houille Blanche Do- maine Universitaire-B.P. 46, 38402, Saint Martin d’Heres, France, stephane.mancini@gipsa-lab.inpg.fr Philippe Marquet LIFL and INRIA Lille Nord-Europe, Parc Scientifique de la Haute Borne, Park Plaza, Bât A, 40 avenue Halley, Villeneuve d’Ascq 59650, France, Philippe.Marquet@lifl.fr Marco Mattavelli SCI-STI-MM, Ecole Polytechnique Fédérale de Lausanne, CH 1015 Lausanne, Switzerland, marco.mattavelli@epfl.ch Marco Mattavelli Microelectronic Systems Laboratory, École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland, marco.mattavelli@epfl.ch Benoît Miramond ETIS Laboratory, UMR CNRS 8051, Université de Cergy- Pontoise/ENSEA, 6, avenue du Ponceau, 95014 Cergy-Pontoise, France, miramond@ensea.fr Romuald Mosqueron SCI-STI-MM, Ecole Polytechnique Fédérale de Lausanne, CH 1015 Lausanne, Switzerland, romuald.mosqueron@epfl.ch
Contributors xi Laurent Moss Ecole Polytechnique de Montréal, Campus de l’Université de Mon- tréal, 2500, chemin de Polytechnique, 2900 boulevard Edouard-Montpetit, Mon- tréal, Quebec H3T 1J4, Canada, Laurent.Moss@polymtl.ca Pengcheng Mu Ministry of Education Key Lab for Intelligent Networks and Net- work Security, School of Electronic and Information Engineering, Xi’an Jiaotong University, Xi’an 710049, P.R. China, pengchengmu@gmail.com Fabrice Muller University of Nice-Sophia Antipolis/LEAT-CNRS, 250 rue Albert Einstein, 06560 Valbonne, France, Fabrice.Muller@unice.fr Jean-François Nezan IETR/Image and Remote Sensing Group, CNRS UMR 6164/INSA Rennes, 20, avenue des Buttes de Coësmes, 35043 Rennes Cedex, France, jnezan@insa-rennes.fr Jose L. Nunez-Yanez University of Bristol, Bristol, UK, J.L.Nunez-Yanez@bristol.ac.uk Braden J. Phillips CHiPTec, Centre for High Performance Integrated Technolo- gies and Systems, The University of Adelaide, Adelaide, Australia, phillips@eleceng.adelaide.edu.au Sébastien Pillement University of Rennes 1, IRISA/INRIA, BP 80518, 6 rue de Kerampont, F22305 Lannion, France Nicolas Pouillon SoC Department, LIP6, 4 place Jussieu, 75252 Paris Cedex, France, nicolas.pouillon@lip6.fr Mickaël Raulet IETR/Image and Remote Sensing Group, CNRS UMR 6164/INSA Rennes, 20, avenue des Buttes de Coësmes, 35043 Rennes Cedex, France, mraulet@insa-rennes.fr Robin Rolland CIME Nanotech, Grenoble, France Olivier Sentieys University of Rennes 1, IRISA/INRIA, BP 80518, 6 rue de Ker- ampont, F22305 Lannion, France Gilles Sicard TIMA Laboratory (CNRS, Grenoble INP, UJF), Grenoble, France Olli Silvén Computer Science and Engineering Laboratory, University of Oulu, Oulu, Finland, olli.silven@ee.oulu.fi Richard Thavot SCI-STI-MM, Ecole Polytechnique Fédérale de Lausanne, CH 1015 Lausanne, Switzerland, richard.thavot@epfl.ch Tomasz Toczek GIPSA-lab, INPG-CNRS, 961 rue de la Houille Blanche Domaine Universitaire-B.P. 46, 38402, Saint Martin d’Heres, France, tomasz.toczek@gipsa-lab.inpg.fr François Verdier ETIS Laboratory, UMR CNRS 8051, Université de Cergy- Pontoise/ENSEA, 6, avenue du Ponceau, 95014 Cergy-Pontoise, France, verdier@ensea.fr
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